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Title: On the interest of carbon-coated plasma reactor for advanced gate stack etching processes

Abstract

In integrated circuit fabrication the most wide spread strategy to achieve acceptable wafer-to-wafer reproducibility of the gate stack etching process is to dry-clean the plasma reactor walls between each wafer processed. However, inherent exposure of the reactor walls to fluorine-based plasma leads to formation and accumulation of nonvolatile fluoride residues (such as AlF{sub x}) on reactor wall surfaces, which in turn leads to process drifts and metallic contamination of wafers. To prevent this while keeping an Al{sub 2}O{sub 3} reactor wall material, a coating strategy must be used, in which the reactor is coated by a protective layer between wafers. It was shown recently that deposition of carbon-rich coating on the reactor walls allows improvements of process reproducibility and reactor wall protection. The authors show that this strategy results in a higher ion-to-neutral flux ratio to the wafer when compared to other strategies (clean or SiOCl{sub x}-coated reactors) because the carbon walls load reactive radical densities while keeping the same ion current. As a result, the etching rates are generally smaller in a carbon-coated reactor, but a highly anisotropic etching profile can be achieved in silicon and metal gates, whose etching is strongly ion assisted. Furthermore, thanks to the lowmore » density of Cl atoms in the carbon-coated reactor, silicon etching can be achieved almost without sidewall passivation layers, allowing fine critical dimension control to be achieved. In addition, it is shown that although the O atom density is also smaller in the carbon-coated reactor, the selectivity toward ultrathin gate oxides is not reduced dramatically. Furthermore, during metal gate etching over high-k dielectric, the low level of parasitic oxygen in the carbon-coated reactor also allows one to minimize bulk silicon reoxidation through HfO{sub 2} high-k gate dielectric. It is then shown that the BCl{sub 3} etching process of the HfO{sub 2} high-k material is highly selective toward the substrate in the carbon-coated reactor, and the carbon-coating strategy thus allows minimizing the silicon recess of the active area of transistors. The authors eventually demonstrate that the carbon-coating strategy drastically reduces on-wafer metallic contamination. Finally, the consumption of carbon from the reactor during the etching process is discussed (and thus the amount of initial deposit that is required to protect the reactor walls) together with the best way of cleaning the reactor after a silicon etching process.« less

Authors:
; ;  [1];  [2]
  1. Freescale Semiconductor Inc., 850 Rue Jean Monnet, 38921 Crolles Cedex (France) and Laboratoire des Technologies de la Microelectronique, CNRS, 17 Rue des Martyrs (c/o CEA-LETI), 38054 Grenoble Cedex 9 (France)
  2. (c/o CEA-LETI), 38054 Grenoble Cedex 9 (France)
Publication Date:
OSTI Identifier:
20979387
Resource Type:
Journal Article
Resource Relation:
Journal Name: Journal of Vacuum Science and Technology. A, International Journal Devoted to Vacuum, Surfaces, and Films; Journal Volume: 25; Journal Issue: 2; Other Information: DOI: 10.1116/1.2464126; (c) 2007 American Vacuum Society; Country of input: International Atomic Energy Agency (IAEA)
Country of Publication:
United States
Language:
English
Subject:
36 MATERIALS SCIENCE; ALUMINIUM OXIDES; BORON CHLORIDES; CARBON; DENSITY; DIELECTRIC MATERIALS; ETCHING; FLUORINE; HAFNIUM OXIDES; INTEGRATED CIRCUITS; IONS; PLASMA; PROTECTIVE COATINGS; SEMICONDUCTOR MATERIALS; SILICON; SURFACE CLEANING; SURFACE CONTAMINATION; THIN FILMS; WALLS

Citation Formats

Ramos, R., Cunge, G., Joubert, O., and Laboratoire des Technologies de la Microelectronique, CNRS, 17 Rue des Martyrs. On the interest of carbon-coated plasma reactor for advanced gate stack etching processes. United States: N. p., 2007. Web. doi:10.1116/1.2464126.
Ramos, R., Cunge, G., Joubert, O., & Laboratoire des Technologies de la Microelectronique, CNRS, 17 Rue des Martyrs. On the interest of carbon-coated plasma reactor for advanced gate stack etching processes. United States. doi:10.1116/1.2464126.
Ramos, R., Cunge, G., Joubert, O., and Laboratoire des Technologies de la Microelectronique, CNRS, 17 Rue des Martyrs. Thu . "On the interest of carbon-coated plasma reactor for advanced gate stack etching processes". United States. doi:10.1116/1.2464126.
@article{osti_20979387,
title = {On the interest of carbon-coated plasma reactor for advanced gate stack etching processes},
author = {Ramos, R. and Cunge, G. and Joubert, O. and Laboratoire des Technologies de la Microelectronique, CNRS, 17 Rue des Martyrs},
abstractNote = {In integrated circuit fabrication the most wide spread strategy to achieve acceptable wafer-to-wafer reproducibility of the gate stack etching process is to dry-clean the plasma reactor walls between each wafer processed. However, inherent exposure of the reactor walls to fluorine-based plasma leads to formation and accumulation of nonvolatile fluoride residues (such as AlF{sub x}) on reactor wall surfaces, which in turn leads to process drifts and metallic contamination of wafers. To prevent this while keeping an Al{sub 2}O{sub 3} reactor wall material, a coating strategy must be used, in which the reactor is coated by a protective layer between wafers. It was shown recently that deposition of carbon-rich coating on the reactor walls allows improvements of process reproducibility and reactor wall protection. The authors show that this strategy results in a higher ion-to-neutral flux ratio to the wafer when compared to other strategies (clean or SiOCl{sub x}-coated reactors) because the carbon walls load reactive radical densities while keeping the same ion current. As a result, the etching rates are generally smaller in a carbon-coated reactor, but a highly anisotropic etching profile can be achieved in silicon and metal gates, whose etching is strongly ion assisted. Furthermore, thanks to the low density of Cl atoms in the carbon-coated reactor, silicon etching can be achieved almost without sidewall passivation layers, allowing fine critical dimension control to be achieved. In addition, it is shown that although the O atom density is also smaller in the carbon-coated reactor, the selectivity toward ultrathin gate oxides is not reduced dramatically. Furthermore, during metal gate etching over high-k dielectric, the low level of parasitic oxygen in the carbon-coated reactor also allows one to minimize bulk silicon reoxidation through HfO{sub 2} high-k gate dielectric. It is then shown that the BCl{sub 3} etching process of the HfO{sub 2} high-k material is highly selective toward the substrate in the carbon-coated reactor, and the carbon-coating strategy thus allows minimizing the silicon recess of the active area of transistors. The authors eventually demonstrate that the carbon-coating strategy drastically reduces on-wafer metallic contamination. Finally, the consumption of carbon from the reactor during the etching process is discussed (and thus the amount of initial deposit that is required to protect the reactor walls) together with the best way of cleaning the reactor after a silicon etching process.},
doi = {10.1116/1.2464126},
journal = {Journal of Vacuum Science and Technology. A, International Journal Devoted to Vacuum, Surfaces, and Films},
number = 2,
volume = 25,
place = {United States},
year = {Thu Mar 15 00:00:00 EDT 2007},
month = {Thu Mar 15 00:00:00 EDT 2007}
}