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Title: High performance FPGA embedded system for machine learning based tracking and trigger in sPhenix and EIC

Abstract

We present a comprehensive end-to-end pipeline to classify triggers versus background events in this paper. This pipeline makes online decisions to select signal data and enables the intelligent trigger system for efficient data collection in the Data Acquisition System (DAQ) of the upcoming sPHENIX and future EIC (Electron-Ion Collider) experiments. Starting from the coordinates of pixel hits that are lightened by passing particles in the detector, the pipeline applies three-stage of event processing (hits clustering, track reconstruction, and trigger detection) and labels all processed events with the binary tag of trigger versus background events. The pipeline consists of deterministic algorithms such as clustering pixels to reduce event size, tracking reconstruction to predict candidate edges, and advanced graph neural network-based models for recognizing the entire jet pattern. In particular, we apply the message-passing graph neural network to predict links between hits and reconstruct tracks and a hierarchical pooling algorithm (DiffPool) to make the graph-level trigger detection. We obtain an impressive performance (≥70% accuracy) for trigger detection with only 3200 neuron weights in the end-to-end pipeline. We deploy the end-to-end pipeline into a field-programmable gate array (FPGA) and accelerate the three stages with speedup factors of 1152, 280, and 21, respectively.

Authors:
; ;
Publication Date:
Research Org.:
Sunrise Technology, Inc., Stonybrook, NY (United States)
Sponsoring Org.:
USDOE Office of Science (SC)
OSTI Identifier:
1979437
DOE Contract Number:  
SC0019518
Resource Type:
Journal Article
Journal Name:
Journal of Instrumentation
Additional Journal Information:
Journal Volume: 17; Journal Issue: 07; Journal ID: ISSN 1748-0221
Publisher:
Institute of Physics (IOP)
Country of Publication:
United States
Language:
English
Subject:
Instruments & Instrumentation

Citation Formats

Xuan, T., Durao, F., and Sun, Y. High performance FPGA embedded system for machine learning based tracking and trigger in sPhenix and EIC. United States: N. p., 2022. Web. doi:10.1088/1748-0221/17/07/c07003.
Xuan, T., Durao, F., & Sun, Y. High performance FPGA embedded system for machine learning based tracking and trigger in sPhenix and EIC. United States. https://doi.org/10.1088/1748-0221/17/07/c07003
Xuan, T., Durao, F., and Sun, Y. 2022. "High performance FPGA embedded system for machine learning based tracking and trigger in sPhenix and EIC". United States. https://doi.org/10.1088/1748-0221/17/07/c07003.
@article{osti_1979437,
title = {High performance FPGA embedded system for machine learning based tracking and trigger in sPhenix and EIC},
author = {Xuan, T. and Durao, F. and Sun, Y.},
abstractNote = {We present a comprehensive end-to-end pipeline to classify triggers versus background events in this paper. This pipeline makes online decisions to select signal data and enables the intelligent trigger system for efficient data collection in the Data Acquisition System (DAQ) of the upcoming sPHENIX and future EIC (Electron-Ion Collider) experiments. Starting from the coordinates of pixel hits that are lightened by passing particles in the detector, the pipeline applies three-stage of event processing (hits clustering, track reconstruction, and trigger detection) and labels all processed events with the binary tag of trigger versus background events. The pipeline consists of deterministic algorithms such as clustering pixels to reduce event size, tracking reconstruction to predict candidate edges, and advanced graph neural network-based models for recognizing the entire jet pattern. In particular, we apply the message-passing graph neural network to predict links between hits and reconstruct tracks and a hierarchical pooling algorithm (DiffPool) to make the graph-level trigger detection. We obtain an impressive performance (≥70% accuracy) for trigger detection with only 3200 neuron weights in the end-to-end pipeline. We deploy the end-to-end pipeline into a field-programmable gate array (FPGA) and accelerate the three stages with speedup factors of 1152, 280, and 21, respectively.},
doi = {10.1088/1748-0221/17/07/c07003},
url = {https://www.osti.gov/biblio/1979437}, journal = {Journal of Instrumentation},
issn = {1748-0221},
number = 07,
volume = 17,
place = {United States},
year = {Fri Jul 01 00:00:00 EDT 2022},
month = {Fri Jul 01 00:00:00 EDT 2022}
}

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