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Title: The RISC processor module for FASTBUS computation applications. Final technical report

Abstract

The FASTBUS system specification for high-energy physics and other data-system applications anticipates the use of multiple, high-performance processor modules for data control and event reduction associated with experiments in the physical sciences. Existing processor designs will be unable to cope with the projected data-reduction and event-handling requirements of the complex experiments planned for the next generation of particle accelerators. Data-handling strategies for experimental physics are evolving from systems based upon a single central computer to those with arrays of high-speed, sophisticated, front-end processing elements. The advent of accelerators such as LEP and LHC, and beyond, is forcing the architecture of these processors toward the simpler RISC designs to enhance both speed and the software-development issue. This report describes the prototype development of a FASTBUS RISC Processor Module (FRPM) for use as a standard processing element in FASTBUS data-acquisition systems under a Phase II SBIR grant through the U.S. Department of Energy, Division of Energy Research. The FRPM hosts a reduced instruction set computer--the SPARCengine-2 by Sun Microcomputer Systems, Inc.--capable of executing 4.2 million floating point instructions per second with a clock of up to 40 MHz. The prototype FRPM supports a port to the FASTBUS crate segment by way ofmore » a standard-logic interface. The FRPM processor operates under a commercially available real-time operating system, and application software can be developed on workstation and mainframe computer systems. We further cover the chronology of the Phase II work, a discussion of the objectives, and our experiences with an ASIC manufacturer in attempting to complete the fabrication of a chip implementing the FASTBUS Master Interface (FMI).« less

Publication Date:
Research Org.:
Scientific Systems International Ltd., Los Alamos, NM (United States)
Sponsoring Org.:
USDOE, Washington, DC (United States)
OSTI Identifier:
192480
Report Number(s):
DOE/ER/80599-17
ON: DE96006048; TRN: 96:001680
DOE Contract Number:  
AC02-88ER80599
Resource Type:
Technical Report
Resource Relation:
Other Information: PBD: [1996]
Country of Publication:
United States
Language:
English
Subject:
43 PARTICLE ACCELERATORS; 99 MATHEMATICS, COMPUTERS, INFORMATION SCIENCE, MANAGEMENT, LAW, MISCELLANEOUS; 42 ENGINEERING NOT INCLUDED IN OTHER CATEGORIES; FASTBUS SYSTEM; DESIGN; ACCELERATORS; DATA ACQUISITION SYSTEMS; ELECTRONIC CIRCUITS; ENGINEERING DRAWINGS

Citation Formats

. The RISC processor module for FASTBUS computation applications. Final technical report. United States: N. p., 1996. Web. doi:10.2172/192480.
. The RISC processor module for FASTBUS computation applications. Final technical report. United States. doi:10.2172/192480.
. Thu . "The RISC processor module for FASTBUS computation applications. Final technical report". United States. doi:10.2172/192480. https://www.osti.gov/servlets/purl/192480.
@article{osti_192480,
title = {The RISC processor module for FASTBUS computation applications. Final technical report},
author = {},
abstractNote = {The FASTBUS system specification for high-energy physics and other data-system applications anticipates the use of multiple, high-performance processor modules for data control and event reduction associated with experiments in the physical sciences. Existing processor designs will be unable to cope with the projected data-reduction and event-handling requirements of the complex experiments planned for the next generation of particle accelerators. Data-handling strategies for experimental physics are evolving from systems based upon a single central computer to those with arrays of high-speed, sophisticated, front-end processing elements. The advent of accelerators such as LEP and LHC, and beyond, is forcing the architecture of these processors toward the simpler RISC designs to enhance both speed and the software-development issue. This report describes the prototype development of a FASTBUS RISC Processor Module (FRPM) for use as a standard processing element in FASTBUS data-acquisition systems under a Phase II SBIR grant through the U.S. Department of Energy, Division of Energy Research. The FRPM hosts a reduced instruction set computer--the SPARCengine-2 by Sun Microcomputer Systems, Inc.--capable of executing 4.2 million floating point instructions per second with a clock of up to 40 MHz. The prototype FRPM supports a port to the FASTBUS crate segment by way of a standard-logic interface. The FRPM processor operates under a commercially available real-time operating system, and application software can be developed on workstation and mainframe computer systems. We further cover the chronology of the Phase II work, a discussion of the objectives, and our experiences with an ASIC manufacturer in attempting to complete the fabrication of a chip implementing the FASTBUS Master Interface (FMI).},
doi = {10.2172/192480},
journal = {},
number = ,
volume = ,
place = {United States},
year = {1996},
month = {2}
}