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Office of Scientific and Technical Information
 

Medium voltage planar DC bus distributed capacitor array

Patent ·
OSTI ID:1892699
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An inverter with a modular bus assembly is described. In various embodiments, the modular bus assembly includes a laminated motherboard and a plurality of capacitor daughtercards. The laminated motherboard can be configured to interface a plurality of phase-leg modules and a plurality of capacitor daughtercards through a plurality of terminals and connectors located on a bottom side or a top side of the laminated motherboard. The laminated motherboard includes a layer stack with a plurality of conductor layers. Each of the plurality of conductor layers is implemented with a net spacing from a neighboring plated through hole (PTH) based at least in part on differences in potential to be applied to each of the plurality of conductor layers as compared to a potential to be applied to the PTH. Embedded shield polygons can be implemented on the laminated motherboard to mitigate surface discharge at surface terminal (PTH/SMT) triple junctions.

Research Organization:
Virginia Polytechnic Inst. and State Univ. (Virginia Tech), Blacksburg, VA (United States)
Sponsoring Organization:
USDOE Office of Energy Efficiency and Renewable Energy (EERE)
DOE Contract Number:
EE0006521
Assignee:
Virginia Tech Intellectual Properties, Inc. (Blacksburg, VA)
Patent Number(s):
11,271,492
Application Number:
16/939,914
OSTI ID:
1892699
Country of Publication:
United States
Language:
English

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