Fiber attach enabled wafer level fanout
A package assembly includes a silicon photonics chip having an optical waveguide exposed at a first side of the chip and an optical fiber coupling region formed along the first side of the chip. The package assembly includes a mold compound structure formed to extend around second, third, and fourth sides of the chip. The mold compound structure has a vertical thickness substantially equal to a vertical thickness of the chip. The package assembly includes a redistribution layer formed over the chip and over a portion of the mold compound structure. The redistribution layer includes electrically conductive interconnect structures to provide fanout of electrical contacts on the chip to corresponding electrical contacts on the redistribution layer. The redistribution layer is formed to leave the optical fiber coupling region exposed. An optical fiber is connected to the optical fiber coupling region in optical alignment with the optical waveguide within the chip.
- Research Organization:
- Ayar Labs, Inc., Santa Clara, CA (United States)
- Sponsoring Organization:
- USDOE
- DOE Contract Number:
- AR0000850
- Assignee:
- Ayar Labs, Inc. (Santa Clara, CA)
- Patent Number(s):
- 11,163,120
- Application Number:
- 16/685,838
- OSTI ID:
- 1860030
- Country of Publication:
- United States
- Language:
- English
Wafer-scale high-density edge coupling for high throughput testing of silicon photonics
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conference | January 2018 |
An O-band Metamaterial Converter Interfacing Standard Optical Fibers to Silicon Nanophotonic Waveguides
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conference | January 2015 |
Low-Cost Interfacing of Fibers to Nanophotonic Waveguides: Design for Fabrication and Assembly Tolerances
|
journal | August 2014 |
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