skip to main content
OSTI.GOV title logo U.S. Department of Energy
Office of Scientific and Technical Information

Title: Method and apparatus for virtualizing the micro-op cache

Patent ·
OSTI ID:1805359
;

Systems, apparatuses, and methods for virtualizing a micro-operation cache are disclosed. A processor includes at least a micro-operation cache, a conventional cache subsystem, a decode unit, and control logic. The decode unit decodes instructions into micro-operations which are then stored in the micro-operation cache. The micro-operation cache has limited capacity for storing micro-operations. When new micro-operations are decoded from pending instructions, existing micro-operations are evicted from the micro-operation cache to make room for the new micro-operations. Rather than being discarded, micro-operations evicted from the micro-operation cache are stored in the conventional cache subsystem. This prevents the original instruction from having to be decoded again on subsequent executions. When the control logic determines that micro-operations for one or more fetched instructions are stored in either the micro-operation cache or the conventional cache subsystem, the control logic causes the decode unit to transition to a reduced-power state.

Research Organization:
Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)
Sponsoring Organization:
USDOE
DOE Contract Number:
AC52-07NA27344; B620717
Assignee:
Advanced Micro Devices, Inc. (Santa Clara, CA)
Patent Number(s):
10,884,751
Application Number:
16/034,844
OSTI ID:
1805359
Resource Relation:
Patent File Date: 07/13/2018
Country of Publication:
United States
Language:
English

References (51)

Advanced processor translation lookaside buffer management in a multithreaded system patent-application March 2005
Dynamic field patchable microarchitecture patent-application December 2001
Method and apparatus for concurrent access to multiple physical caches patent October 1998
Accelerated code optimizer for a multiengine microprocessor patent January 2019
System for cache space allocation using selective addressing patent July 1992
Precise counter hardware for microcode loops patent May 2011
Dual operating system computer patent January 1994
Method and apparatus for modifying microcode in a distributed nodal network while the network continues operation patent July 1997
An Allocation and Issue Stage for Reordering a Microinstruction Sequence into a Optimized Microinstruction Sequence to Implement and Instruction Set agnostic Runtime Architecture patent-application January 2016
Precise error handling in a fine grain multithreaded multicore processor patent May 2008
Microprocessor that Performs X86 ISA and ARM ISA Machine Language Program Instruction by Hardware Translation Into Microinstructions Executed by Common Execution Pipeline patent-application October 2012
Preventing access to secure area of a cache patent May 2002
Method and apparatus for pipeline inclusion and instruction restarts in a micro-op cache of a processor patent-application June 2010
Flash memory controller with updateable microcode patent June 2004
Low Latency Synchronization for Operation Cache and Instruction Cache Fetching and Decoding Instructions patent-application December 2019
Microprocessor configured to selectively invoke a microcode DSP function or a program subroutine in response to a target address value of branch instruction patent January 1999
Microprocessor accelerated code optimizer patent December 2019
Decoding a Complex Program Instruction Corresponding to Multiple Micro-Operations patent-application April 2015
Method and apparatus for pipeline inclusion and instruction restarts in a micro-op cache of a processor patent February 2012
Microprocessor circuits, systems, and methods using a combined writeback queue and victim cache patent March 2000
Method and system for restricting the load of physical address translations of virtual addresses patent June 2004
Mechanism to remove stale branch predictions at a microprocessor patent-application December 2004
Computer system patent-application August 2006
Accelerated Code Optimizer for Multiengine Microprocessor patent-application July 2015
Microprocessor Accelerated Code Optimizer patent-application January 2017
Apparatus and method for microcode patching for generating a next address patent October 2000
TLB with resource ID field patent-application June 2002
Single chip microprocessor circuits, systems, and methods for self-loading patch micro-operation codes and patch microinstruction codes patent September 1999
Microprocessor with customer code store patent-application January 2006
Microprocessor Accelerated Code Optimizer and Dependency Reordering Method patent-application November 2014
Micro-Operation Cache Using Predictive Allocation patent-application July 2020
Hardware Processors and Methods for Extended Microcode Patching patent-application July 2020
Method and apparatus for dedicating cache entries to certain streams for performance optimization patent-application August 2005
Code Reuse and Locality Hinting patent-application July 2009
Method and apparatus for performing microcode paging during instruction execution in an instruction processor patent August 1998
microprocessor with Private Microcode Ram patent-application October 2008
Compressing microcode patent August 2006
Method and apparatus for testing microarchitectural features by using tests written in microcode patent November 2003
System for performing input and output operations to and from a processor patent September 2000
Emulation of interrupt control mechanism in a multiprocessor system patent March 1999
Method to remove stale branch predictions for an instruction prior to execution within a microprocessor patent August 2010
Using Loop Exit Prediction to Accelerate or Suppress Loop Mode of a Processor patent-application March 2020
Data processing system having unique multilevel microcode architecture patent February 1990
Microprocessor that performs X86 ISA and arm ISA machine language program instructions by hardware translation into microinstructions executed by common execution pipeline patent November 2014
Method And Apparatus For Virtualized Microcode Sequencing patent-application December 2011
Caching of microcode emulation memory patent June 2010
Code reuse and locality hinting patent April 2014
Microprocessor Accelerated Code Optimizer patent-application February 2015
Method and apparatus for microcode loading in a multi-nodal network exhibiting distributed control patent September 1997
Decoding a complex program instruction corresponding to multiple micro-operations patent April 2018
Method and Apparatus for Context Switching and Synchronization patent-application October 2008

Similar Records

Related Subjects