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Title: Characterization of a gigabit transceiver for the ATLAS inner tracker pixel detector readout upgrade

Journal Article · · Journal of Instrumentation
 [1];  [2];  [3];  [3];  [1];  [4];  [5];  [2];  [2];  [4];  [5];  [2];  [2];  [3];  [2]
  1. Central China Normal Univ., Hubei (China); Southern Methodist Univ., Dallas, TX (United States)
  2. Southern Methodist Univ., Dallas, TX (United States)
  3. Central China Normal Univ., Hubei (China)
  4. European Organization for Nuclear Research (CERN), Geneva (Switzerland)
  5. KU Leuven (Switzerland)
+ Show Author Affiliations

We present a gigabit transceiver prototype Application Specific Integrated Circuit (ASIC), GBCR, for the ATLAS Inner Tracker (ITk) Pixel detector readout upgrade. GBCR is designed in a 65-nm CMOS technology and consists of four upstream receiver channels, a downstream transmitter channel, and an Inter-Integrated Circuit (I2C) slave. The upstream channels receive the data at 5.12 Gbps passing through 5-meter 34-American Wire Gauge (AWG) Twin-axial (Twinax) cables, equalize and retime them with a recovered clock, and then drive an optical transmitter. The downstream channel receives the data at 2.56 Gbps from an optical receiver and drives the cable as same as the upstream channels. The jitter of the upstream channel output is measured to be 35 ps (peak-peak) when the Clock-Data Recovery (CDR) module is turned on and the jitter of the downstream channel output after the cable is 138 ps (peak-peak). The power consumption of each upstream channel is 72 mW when the CDR module is turned on and the downstream channel consumes 27 mW. GBCR survives the total ionizing dose of 200 kGy.

Research Organization:
Harvard Univ., Cambridge, MA (United States)
Sponsoring Organization:
USDOE Office of Science (SC), High Energy Physics (HEP)
Grant/Contract Number:
SC0007881; AC02-05CH11231
OSTI ID:
1685045
Journal Information:
Journal of Instrumentation, Vol. 15, Issue 03; ISSN 1748-0221
Publisher:
Institute of Physics (IOP)Copyright Statement
Country of Publication:
United States
Language:
English

References (8)

A 3-GHz 32-dB CMOS limiting amplifier for SONET OC-48 receivers journal December 2000
A 12 GHz low-jitter LC-VCO PLL in 130 nm CMOS journal March 2015
A 4.9-GHz low power, low jitter, LC phase locked loop journal December 2010
A 10-Gb/s CMOS clock and data recovery circuit with a half-rate linear phase detector journal May 2001
A low noise clock generator for high-resolution time-to-digital convertors journal February 2016
Equalization and Clock and Data Recovery Techniques for 10-Gb/s CMOS Serial-Link Receivers journal September 2007
A New Adaptive Technique for Transmitter Pre-Emphasis and Receiver Equalization in a High-Speed Backplane Environment conference January 2006
A 2.56-GHz SEU Radiation Hard $LC$ -Tank VCO for High-Speed Communication Links in 65-nm CMOS Technology journal January 2018

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Related Subjects

47 OTHER INSTRUMENTATION
Analogue electronic circuits
Electronic detector readout concepts (solid-state)
Front-end electronics for detector readout
VLSI circuits