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Title: Setting operating points for circuits in an integrated circuit chip using an integrated voltage regulator power loss model

Patent ·
OSTI ID:1632554

An apparatus includes an integrated circuit chip with a set of circuits having two or more subsets of circuits; an external voltage regulator separate from the integrated circuit chip; two or more integrated voltage regulators on the integrated circuit chip that each provide an input voltage to a respective subset of the circuits; and a controller. The controller determines, using an integrated voltage regulator power loss model, an electrical power loss for the integrated voltage regulators for a first combination of operating points for the subsets of the circuits. The controller then determines, based on the electrical power loss, a second combination of operating points for the subsets of the circuits that includes an adjustment to an operating point for at least one of the subsets of the circuits that compensates for an electrical power loss of the corresponding integrated voltage regulator. The controller sets an operating point of each of the subsets of the circuits based on the second combination of operating points.

Research Organization:
Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)
Sponsoring Organization:
USDOE
DOE Contract Number:
AC52-07NA27344; B620717
Assignee:
Advanced Micro Devices, Inc. (Santa Clara, CA)
Patent Number(s):
10,560,022
Application Number:
16/440,838
OSTI ID:
1632554
Resource Relation:
Patent File Date: 06/13/2019
Country of Publication:
United States
Language:
English

References (2)

Dynamic voltage adjust circuits and methods patent-application May 2015
Communication Apparatus and Control Method Thereof patent-application October 2011

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