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Title: CDFG Extraction Tool for LLVM.

Abstract

With the dawn of the exascale era, computer scientists and engineers are faced with tremendous challenges across all facets of the HPC system scalability, performance, reliability, and power consumption. In particular, the power-performance benet from one processor generation to the next is seeing ever-diminishing returns and will require fundamental changes in the way we approach computation. In fact, it is likely that different applications will require different types of accelerators in order to meet power, performance, and reliability requirements at scale. One potential type of accelerator, a dataow architecture, diverges from the traditional sequentially executed instruction model into one that reects the inherent instruction-level parallelism in a program. This work presents the intial steps toward a tool that can extract the control-dataow graph from an application. This page intentionally left blank.

Authors:
; ;
Publication Date:
Research Org.:
Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)
Sponsoring Org.:
USDOE National Nuclear Security Administration (NNSA)
OSTI Identifier:
1598439
Report Number(s):
SAND2020-0937
683468
DOE Contract Number:  
AC04-94AL85000
Resource Type:
Technical Report
Country of Publication:
United States
Language:
English

Citation Formats

Hughes, Clayton, Hammond, Simon David, and Hoekstra, Robert J. CDFG Extraction Tool for LLVM.. United States: N. p., 2020. Web. doi:10.2172/1598439.
Hughes, Clayton, Hammond, Simon David, & Hoekstra, Robert J. CDFG Extraction Tool for LLVM.. United States. doi:10.2172/1598439.
Hughes, Clayton, Hammond, Simon David, and Hoekstra, Robert J. Wed . "CDFG Extraction Tool for LLVM.". United States. doi:10.2172/1598439. https://www.osti.gov/servlets/purl/1598439.
@article{osti_1598439,
title = {CDFG Extraction Tool for LLVM.},
author = {Hughes, Clayton and Hammond, Simon David and Hoekstra, Robert J.},
abstractNote = {With the dawn of the exascale era, computer scientists and engineers are faced with tremendous challenges across all facets of the HPC system scalability, performance, reliability, and power consumption. In particular, the power-performance benet from one processor generation to the next is seeing ever-diminishing returns and will require fundamental changes in the way we approach computation. In fact, it is likely that different applications will require different types of accelerators in order to meet power, performance, and reliability requirements at scale. One potential type of accelerator, a dataow architecture, diverges from the traditional sequentially executed instruction model into one that reects the inherent instruction-level parallelism in a program. This work presents the intial steps toward a tool that can extract the control-dataow graph from an application. This page intentionally left blank.},
doi = {10.2172/1598439},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2020},
month = {1}
}