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Title: A Low Power, High Speed Readout for Pixel Detectors Based on an Arbitration Tree

Abstract

A low-power, high-speed arbitration tree for pixel detector readout is presented. The synchronized, binary tree priority encoder establishes a position dependent priority list at the start of every time frame. Pixels that indicate the presence of data for readout, are sequentially granted access to a shared bus for data transfer to the periphery, without the use of an additional global strobe signal. It can be used for either full frame imaging or zero-suppressed readout, in which case it can simultaneously generate the pixel address. To increase the readout frame rate, the pixel array is subdivided into two halves, which allows interleaved latching of data at the output serializer. The design was implemented in a 65 nm LP-CMOS process for the readout of a 64 x 64 pixel array. Measurement results demonstrate a deadtime-less, full frame imaging rate of ~50 kfps, achieved with a dedicated output for every (32 x 32) 1024 pixels and for a pixel data packet of 11 bits, with no bit errors detected over 1000 frames. The measured energy per bit is 0.94 pJ.

Authors:
ORCiD logo [1];  [2];  [2];  [2]
  1. Fermilab
  2. Northwestern U. (main)
Publication Date:
Research Org.:
Fermi National Accelerator Lab. (FNAL), Batavia, IL (United States)
Sponsoring Org.:
USDOE Office of Science (SC), High Energy Physics (HEP) (SC-25)
OSTI Identifier:
1576525
Report Number(s):
FERMILAB-PUB-19-188-PPD
oai:inspirehep.net:1766999
DOE Contract Number:  
AC02-07CH11359
Resource Type:
Journal Article
Journal Name:
TBD
Additional Journal Information:
Journal Name: TBD
Country of Publication:
United States
Language:
English
Subject:
46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND TECHNOLOGY

Citation Formats

Fahim, Farah, Joshi, Siddhartha, Ogrenci-Memik, Seda, and Mohseni, Hooman. A Low Power, High Speed Readout for Pixel Detectors Based on an Arbitration Tree. United States: N. p., 2019. Web.
Fahim, Farah, Joshi, Siddhartha, Ogrenci-Memik, Seda, & Mohseni, Hooman. A Low Power, High Speed Readout for Pixel Detectors Based on an Arbitration Tree. United States.
Fahim, Farah, Joshi, Siddhartha, Ogrenci-Memik, Seda, and Mohseni, Hooman. Tue . "A Low Power, High Speed Readout for Pixel Detectors Based on an Arbitration Tree". United States. https://www.osti.gov/servlets/purl/1576525.
@article{osti_1576525,
title = {A Low Power, High Speed Readout for Pixel Detectors Based on an Arbitration Tree},
author = {Fahim, Farah and Joshi, Siddhartha and Ogrenci-Memik, Seda and Mohseni, Hooman},
abstractNote = {A low-power, high-speed arbitration tree for pixel detector readout is presented. The synchronized, binary tree priority encoder establishes a position dependent priority list at the start of every time frame. Pixels that indicate the presence of data for readout, are sequentially granted access to a shared bus for data transfer to the periphery, without the use of an additional global strobe signal. It can be used for either full frame imaging or zero-suppressed readout, in which case it can simultaneously generate the pixel address. To increase the readout frame rate, the pixel array is subdivided into two halves, which allows interleaved latching of data at the output serializer. The design was implemented in a 65 nm LP-CMOS process for the readout of a 64 x 64 pixel array. Measurement results demonstrate a deadtime-less, full frame imaging rate of ~50 kfps, achieved with a dedicated output for every (32 x 32) 1024 pixels and for a pixel data packet of 11 bits, with no bit errors detected over 1000 frames. The measured energy per bit is 0.94 pJ.},
doi = {},
journal = {TBD},
number = ,
volume = ,
place = {United States},
year = {2019},
month = {1}
}