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Title: Essential Signal Simulation Enabled by Netlist Transforms (ESSENT) v1.0

Abstract

Hardware simulation is an indispensable tool for designing chips as well as researching future architectures. Unfortunately, the slow rate of simulation can often bottleneck the design process, as designers must wait to see the results of a simulation before changing the design and starting a new simulation. The Essential Signal Simulation Enabled by Netlist Transforms (ESSENT) is a tool designed to accelerate hardware simulations. ESSENT takes in a design, uses graph algorithms to identify opportunities for conditional execution, and generates a simulator that leverages these opportunities. The generated simulator produces the exact same simulation results that would be returned by an unoptimized simulator, but in substantially less time. For input, ESSENT takes in designs formatted in FIRRTL (an open format).

Developers:
 [1]
  1. Lawrence Berkeley National Lab. (LBNL), Berkeley, CA (United States)
Release Date:
Project Type:
Open Source, Publicly Available Repository
Software Type:
Scientific
Licenses:
BSD 3-clause "New" or "Revised" License
Sponsoring Org.:
USDOE

Primary Award/Contract Number:
AC02-05CH11231
Code ID:
31844
Site Accession Number:
2019-127
Research Org.:
Lawrence Berkeley National Lab. (LBNL), Berkeley, CA (United States)
Country of Origin:
United States

Citation Formats

Beamer, Scott, and USDOE. Essential Signal Simulation Enabled by Netlist Transforms (ESSENT) v1.0. Computer software. https://www.osti.gov//servlets/purl/1572345. USDOE. 3 Jul. 2019. Web. doi:10.11578/dc.20191029.3.
Beamer, Scott, & USDOE. (2019, July 3). Essential Signal Simulation Enabled by Netlist Transforms (ESSENT) v1.0 [Computer software]. https://www.osti.gov//servlets/purl/1572345. doi:10.11578/dc.20191029.3.
Beamer, Scott, and USDOE. Essential Signal Simulation Enabled by Netlist Transforms (ESSENT) v1.0. Computer software. July 3, 2019. https://www.osti.gov//servlets/purl/1572345. doi:10.11578/dc.20191029.3.
@misc{osti_1572345,
title = {Essential Signal Simulation Enabled by Netlist Transforms (ESSENT) v1.0},
author = {Beamer, Scott and USDOE},
abstractNote = {Hardware simulation is an indispensable tool for designing chips as well as researching future architectures. Unfortunately, the slow rate of simulation can often bottleneck the design process, as designers must wait to see the results of a simulation before changing the design and starting a new simulation. The Essential Signal Simulation Enabled by Netlist Transforms (ESSENT) is a tool designed to accelerate hardware simulations. ESSENT takes in a design, uses graph algorithms to identify opportunities for conditional execution, and generates a simulator that leverages these opportunities. The generated simulator produces the exact same simulation results that would be returned by an unoptimized simulator, but in substantially less time. For input, ESSENT takes in designs formatted in FIRRTL (an open format).},
url = {https://www.osti.gov//servlets/purl/1572345},
doi = {10.11578/dc.20191029.3},
year = {2019},
month = {7},
note =
}

Software:
Publicly Accessible Repository
https://github.com/ucsc-vama/essent

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