Variable loop gain using excessive regeneration for a delayed wide-area control system

Patent · 16 July 2019

OSTI ID:1568616

Roberson, Dakota; O'Brien, John F.

Disclosed are methods and systems for adjusting a High Voltage Direct Current (HVDC) compensator output signal to an HVDC system to reduce control loop modulus due to excessive time delay of sensor measurements. Two different time windows, a Short-Time Variance Window (STVW) and an Extended-Time Variance Window (ETVW) may be examined for detection of increased energy. To detect increased energy the HVDC compensator output signal may be passed through a bandpass filter, then variances for the STVW and ETVW may be generated to produce corresponding test statistics. The STVW and ETVW test statistics may be compared to hypothesis test thresholds and have binary logic based on the hypothesis test comparisons used to generate a gain. The gain may then be multiplied times the original HVDC feedback compensator output such that the adjusted HVDC feedback compensator output reduces the control loop modulus when applied to the HVDC system.

• Research Organization: University of Wyoming, Laramie, WY (United States)
• Sponsoring Organization: USDOE
• DOE Contract Number: SC0012671
• Assignee: University of Wyoming (Laramie, WY)
• Patent Number(s): 10,355,485
• Application Number: 15/959,039
• OSTI ID: 1568616
• Country of Publication: United States
• Language: English