skip to main content
OSTI.GOV title logo U.S. Department of Energy
Office of Scientific and Technical Information

Title: Evaluating Burst Buffer Placement in HPC Systems

Abstract

Burst buffers (BBs) are increasingly exploited in contemporary supercomputers to bridge the performance gap between compute and storage systems. The design of BBs, particularly the placement of these devices and the underlying network topology, impacts both performance and cost. As the cost of other components such as memory and accelerators is increasing, it is becoming more important that HPC centers provision BBs tailored to their workloads.This work contributes a provisioning system to provide accurate, multi-tenant simulations that model realistic application and storage workloads from HPC systems. The framework aids HPC centers in modeling their workloads against multiple network and BB configurations rapidly. In experiments with our framework, we provide a comparison of representative Oak Ridge Leadership Computing Facility (OLCF) I/O workloads against multiple BB designs. We analyze the impact of these designs on latency, I/O phase lengths, contention for network and storage devices, and choice of network topology.

Authors:
 [1]; ORCiD logo [2];  [3]; ORCiD logo [2]; ORCiD logo [2];  [4]
  1. North Carolina State University
  2. ORNL
  3. North Carolina State University (NCSU), Raleigh
  4. Argonne National Laboratory
Publication Date:
Research Org.:
Oak Ridge National Lab. (ORNL), Oak Ridge, TN (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1566958
DOE Contract Number:  
AC05-00OR22725
Resource Type:
Conference
Resource Relation:
Conference: IEEE International Conference on Cluster Computing (IEEE Cluster 2019) - Albuquerque, New Mexico, United States of America - 9/23/2019 5:00:00 PM-9/26/2019 12:00:00 PM
Country of Publication:
United States
Language:
English

Citation Formats

Khetawat, Harsh, Zimmer, Christopher, Mueller, Frank, Atchley, Scott, Vazhkudai, Sudharshan, and Mubarak, Misbah. Evaluating Burst Buffer Placement in HPC Systems. United States: N. p., 2019. Web.
Khetawat, Harsh, Zimmer, Christopher, Mueller, Frank, Atchley, Scott, Vazhkudai, Sudharshan, & Mubarak, Misbah. Evaluating Burst Buffer Placement in HPC Systems. United States.
Khetawat, Harsh, Zimmer, Christopher, Mueller, Frank, Atchley, Scott, Vazhkudai, Sudharshan, and Mubarak, Misbah. Sun . "Evaluating Burst Buffer Placement in HPC Systems". United States. https://www.osti.gov/servlets/purl/1566958.
@article{osti_1566958,
title = {Evaluating Burst Buffer Placement in HPC Systems},
author = {Khetawat, Harsh and Zimmer, Christopher and Mueller, Frank and Atchley, Scott and Vazhkudai, Sudharshan and Mubarak, Misbah},
abstractNote = {Burst buffers (BBs) are increasingly exploited in contemporary supercomputers to bridge the performance gap between compute and storage systems. The design of BBs, particularly the placement of these devices and the underlying network topology, impacts both performance and cost. As the cost of other components such as memory and accelerators is increasing, it is becoming more important that HPC centers provision BBs tailored to their workloads.This work contributes a provisioning system to provide accurate, multi-tenant simulations that model realistic application and storage workloads from HPC systems. The framework aids HPC centers in modeling their workloads against multiple network and BB configurations rapidly. In experiments with our framework, we provide a comparison of representative Oak Ridge Leadership Computing Facility (OLCF) I/O workloads against multiple BB designs. We analyze the impact of these designs on latency, I/O phase lengths, contention for network and storage devices, and choice of network topology.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2019},
month = {9}
}

Conference:
Other availability
Please see Document Availability for additional information on obtaining the full-text document. Library patrons may search WorldCat to identify libraries that hold this conference proceeding.

Save / Share: