System and method for hardware scheduling of indexed barriers
A method and a system are provided for hardware scheduling of indexed barrier instructions. Execution of a plurality of threads to process instructions of a program that includes a barrier instruction is initiated and when each thread reaches the barrier instruction, the thread pauses execution of the instructions. A first sub-group of threads in the plurality of threads is associated with a first sub-barrier index and a second sub-group of threads in the plurality of threads is associated with a second sub-barrier index. When the barrier instruction can be scheduled for execution, threads in the first sub-group are executed serially and threads in the second sub-group are executed serially and at least one thread in the first sub-group is executed in parallel with at least one thread in the second sub-group.
- Research Organization:
- NVIDIA Corp., Santa Clara, CA (United States)
- Sponsoring Organization:
- USDOE
- DOE Contract Number:
- B599861
- Assignee:
- NVIDIA Corporation (Santa Clara, CA)
- Patent Number(s):
- 9,442,755
- Application Number:
- 13/844,541
- OSTI ID:
- 1531942
- Resource Relation:
- Patent File Date: 2013-03-15
- Country of Publication:
- United States
- Language:
- English
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