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Title: Dynamic memory remapping to reduce row-buffer conflicts

Patent ·
OSTI ID:1531406

A data processing system includes a memory that includes a first memory bank and a second memory bank. The data processing system also includes a conflict detector connected to the memory and adapted to receive memory access information. The conflict detector tracks memory access statistics of the first memory bank, and determines if the first memory bank contains frequent row conflicts. The conflict detector also remaps a frequent row conflict in the first memory bank to the second memory bank. An indirection table is connected to the conflict detector and adapted to receive a memory access request, and redirects an address into a dynamically selected physical memory address in response to a remapping of the frequent row conflict to the second memory bank.

Research Organization:
Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)
Sponsoring Organization:
USDOE
DOE Contract Number:
AC52-07NA27344; B609201
Assignee:
Advanced Micro Devices, Inc. (Santa Clara, CA)
Patent Number(s):
10,198,369
Application Number:
15/469,071
OSTI ID:
1531406
Resource Relation:
Patent File Date: 2017-03-24
Country of Publication:
United States
Language:
English

References (5)

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System, apparatus, and method for transparent page level instruction translation patent May 2016
A simple algorithm for finding frequent elements in streams and bags journal March 2003
Arbiter system for central processing unit having dual dominoed encoders for four instruction issue per machine cycle patent June 2001