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Title: Register files for I/O packet compression

Patent ·
OSTI ID:1531363
; ;

Systems, apparatuses, and methods for reducing inter-node bandwidth are contemplated. A computer system includes requesting nodes sending transactions to target nodes. A requesting node sends a packet that includes a register identifier (ID) in place of a data value in the packet. The register ID indicates a register in the target node storing the data value. The register ID uses fewer bits in the packet than the data value. The data value may be a memory address referencing a memory location in the target node. The received packet may also include an opcode indicating an operation to perform on the targeted data value.

Research Organization:
Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)
Sponsoring Organization:
USDOE
DOE Contract Number:
AC52-07NA27344; B608045
Assignee:
Advanced Micro Devices, Inc. (Santa Clara, CA)
Patent Number(s):
10,079,916
Application Number:
15/138,485
OSTI ID:
1531363
Resource Relation:
Patent File Date: 2016-04-26
Country of Publication:
United States
Language:
English

References (10)

High Performance, Scalable Multi Chip Interconnect patent-application May 2014
Optimized Thread Scheduling via Hardware Performance Monitoring patent-application March 2011
Transaction Processing Using Multiple Protocol Engines patent-application January 2014
Cluster membership monitor patent-application February 2003
Managing Bandwidth Allocation in a Processing Node Using Distributed Arbitration patent-application November 2012
High performance IP processor using RDMA patent May 2017
Node device patent July 1991
Processing of multicast traffic in computer networks patent-application September 2014
Shared resources in a chip multiprocessor patent June 2008
Method and Apparatus for Communicating Between Threads patent-application January 2008

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