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Title: Analyzing the suitability of contemporary 3D-stacked PIM architectures for HPC scientific applications

Abstract

Scaling off-chip bandwidth is challenging due to fundamental limitations, such as a fixed pin count and plateauing signaling rates. Recently, vendors have turned to 2.5D and 3D stacking to closely integrate system components. Interestingly, these technologies can integrate a logic layer under multiple memory dies, enabling computing capability inside a memory stack. This trend in stacking is making PIM architectures commercially viable. In this work, we investigate the suitability of offloading kernels in scientific applications onto 3D stacked PIM architectures. We evaluate several hardware constraints resulted from the stacked structure. We perform extensive simulation experiments and in-depth analysis to quantify the impact of application locality in TLBs, data caches, and memory stacks. Our results also identify design optimization areas in software and hardware for HPC scientific applications.

Authors:
 [1]; ORCiD logo [1]; ORCiD logo [1];  [2];  [3]
  1. ORNL
  2. Intel Labs
  3. KTH Royal Institute of Technology, Stockholm, Sweden
Publication Date:
Research Org.:
Oak Ridge National Lab. (ORNL), Oak Ridge, TN (United States)
Sponsoring Org.:
USDOE Office of Science (SC)
OSTI Identifier:
1530065
DOE Contract Number:  
AC05-00OR22725
Resource Type:
Conference
Resource Relation:
Conference: International Conference on Computing Frontiers - Alghero, , Italy - 4/30/2019 4:00:00 AM-5/2/2019 4:00:00 AM
Country of Publication:
United States
Language:
English

Citation Formats

Peng, Ivy Bo, Vetter, Jeffrey S., Moore, Shirley V., Joydeep, Rakshit, and Markidis, Stefano. Analyzing the suitability of contemporary 3D-stacked PIM architectures for HPC scientific applications. United States: N. p., 2019. Web. doi:10.1145/3310273.3322831.
Peng, Ivy Bo, Vetter, Jeffrey S., Moore, Shirley V., Joydeep, Rakshit, & Markidis, Stefano. Analyzing the suitability of contemporary 3D-stacked PIM architectures for HPC scientific applications. United States. doi:10.1145/3310273.3322831.
Peng, Ivy Bo, Vetter, Jeffrey S., Moore, Shirley V., Joydeep, Rakshit, and Markidis, Stefano. Mon . "Analyzing the suitability of contemporary 3D-stacked PIM architectures for HPC scientific applications". United States. doi:10.1145/3310273.3322831. https://www.osti.gov/servlets/purl/1530065.
@article{osti_1530065,
title = {Analyzing the suitability of contemporary 3D-stacked PIM architectures for HPC scientific applications},
author = {Peng, Ivy Bo and Vetter, Jeffrey S. and Moore, Shirley V. and Joydeep, Rakshit and Markidis, Stefano},
abstractNote = {Scaling off-chip bandwidth is challenging due to fundamental limitations, such as a fixed pin count and plateauing signaling rates. Recently, vendors have turned to 2.5D and 3D stacking to closely integrate system components. Interestingly, these technologies can integrate a logic layer under multiple memory dies, enabling computing capability inside a memory stack. This trend in stacking is making PIM architectures commercially viable. In this work, we investigate the suitability of offloading kernels in scientific applications onto 3D stacked PIM architectures. We evaluate several hardware constraints resulted from the stacked structure. We perform extensive simulation experiments and in-depth analysis to quantify the impact of application locality in TLBs, data caches, and memory stacks. Our results also identify design optimization areas in software and hardware for HPC scientific applications.},
doi = {10.1145/3310273.3322831},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2019},
month = {4}
}

Conference:
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