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Title: Helios Phase I Final Report

Abstract

During the Phase I Small Business Innovative Research (SBIR) effort, Idaho Scientific conducted research to develop and demonstrate Helios, a novel secure processor architecture designed to address the inherent vulnerabilities in modern computer processors. The result of this effort is a prototype implementation on a Risc-V processor hardened against cyber-attack. The prototype was demonstrated within a field programable gate array (FPGA).

Authors:
 [1]
  1. Idaho Scientific
Publication Date:
Research Org.:
Idaho Scientific
Sponsoring Org.:
USDOE Office of Energy Efficiency and Renewable Energy (EERE), Solar Energy Technologies Office (EE-4S)
OSTI Identifier:
1513580
Report Number(s):
Final Report: Helios Phase I
DOE Contract Number:  
SC0018829
Resource Type:
Technical Report
Resource Relation:
Related Information: The U.S. is transitioning to a heavy reliance on distributed energy resources (DER). This includes solar and wind assets owned by utility, industry, and residential operators. Recent initiatives including IEEE 2030.7, IEC 61850-7-420, and California’s Rule 21 are driving increased connectivity between DER control systems, and utility command and control networks. These systems are designed to accommodate utility control of DER for the purpose of grid stabilization. The risk associated with these efforts include increase exposure to cyber-attacks.
Country of Publication:
United States
Language:
English
Subject:
24 POWER TRANSMISSION AND DISTRIBUTION; Secure Processor, Cyber Security, Smart Inverter

Citation Formats

Reese, Dale. Helios Phase I Final Report. United States: N. p., 2019. Web.
Reese, Dale. Helios Phase I Final Report. United States.
Reese, Dale. Tue . "Helios Phase I Final Report". United States.
@article{osti_1513580,
title = {Helios Phase I Final Report},
author = {Reese, Dale},
abstractNote = {During the Phase I Small Business Innovative Research (SBIR) effort, Idaho Scientific conducted research to develop and demonstrate Helios, a novel secure processor architecture designed to address the inherent vulnerabilities in modern computer processors. The result of this effort is a prototype implementation on a Risc-V processor hardened against cyber-attack. The prototype was demonstrated within a field programable gate array (FPGA).},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2019},
month = {1}
}

Technical Report:
Other availability
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