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Title: Trinity benchmarks on the Intel Xeon Phi (Knights Corner).

Abstract

This report documents the early experiences with porting and performance analysis of the Tri-Lab Trinity benchmark applications on Intel Xeon Phi (Knights Corner) (KNC) processor. KNC, the second generation of the Intel Many Integrated Core (MIC) architectures, uses a large number of small P54C-x86 cores with wide vector units and is deployed as PCI bus attached process accelerators. Sandia has experimental test beds of small InifiniBand clusters and workstations to investigate the performance of the MIC architecture. On these experimental test beds the programming models that may be investigated are (3z(Boffload(3y(B, (3z(Bsymmetric(3y (Band (3z(Bnative(3y. (BAmong these program usage models our primary interest is in the so called (3z(Bnative(3y (Bmode, because the planned Trinity system to be deployed in 2016 using the next generation MIC processor architecture called Knights Landing would be self-hosted. Trinity / NERSC-8 benchmark programs cover a variety of scientific disciplines and they were used to guide the procurement of these systems. Architectures such as the Intel MIC are well suited to study evolving processor architectures and a usage model commonly referred to as MPI + X that facilitates migration of our applications to use both coarse grain and fine grain parallelism. Our focus with the applications selectedmore » is on the efficacy of algorithms in these applications to take advantage of features like: large number of cores, wide vector units, higher-bandwidth and deeper memory sub-system. This is a first step towards understanding applications, algorithms and programming environments for Trinity and future exascale computing systems.« less

Authors:
; ;
Publication Date:
Research Org.:
Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)
Sponsoring Org.:
USDOE National Nuclear Security Administration (NNSA)
OSTI Identifier:
1504115
Report Number(s):
SAND2015-0454
562263
DOE Contract Number:  
AC04-94AL85000
Resource Type:
Technical Report
Country of Publication:
United States
Language:
English

Citation Formats

Rajan, Mahesh, Doerfler, Douglas W., and Hammond, Simon David. Trinity benchmarks on the Intel Xeon Phi (Knights Corner).. United States: N. p., 2015. Web. doi:10.2172/1504115.
Rajan, Mahesh, Doerfler, Douglas W., & Hammond, Simon David. Trinity benchmarks on the Intel Xeon Phi (Knights Corner).. United States. doi:10.2172/1504115.
Rajan, Mahesh, Doerfler, Douglas W., and Hammond, Simon David. Thu . "Trinity benchmarks on the Intel Xeon Phi (Knights Corner).". United States. doi:10.2172/1504115. https://www.osti.gov/servlets/purl/1504115.
@article{osti_1504115,
title = {Trinity benchmarks on the Intel Xeon Phi (Knights Corner).},
author = {Rajan, Mahesh and Doerfler, Douglas W. and Hammond, Simon David},
abstractNote = {This report documents the early experiences with porting and performance analysis of the Tri-Lab Trinity benchmark applications on Intel Xeon Phi (Knights Corner) (KNC) processor. KNC, the second generation of the Intel Many Integrated Core (MIC) architectures, uses a large number of small P54C-x86 cores with wide vector units and is deployed as PCI bus attached process accelerators. Sandia has experimental test beds of small InifiniBand clusters and workstations to investigate the performance of the MIC architecture. On these experimental test beds the programming models that may be investigated are (3z(Boffload(3y(B, (3z(Bsymmetric(3y (Band (3z(Bnative(3y. (BAmong these program usage models our primary interest is in the so called (3z(Bnative(3y (Bmode, because the planned Trinity system to be deployed in 2016 using the next generation MIC processor architecture called Knights Landing would be self-hosted. Trinity / NERSC-8 benchmark programs cover a variety of scientific disciplines and they were used to guide the procurement of these systems. Architectures such as the Intel MIC are well suited to study evolving processor architectures and a usage model commonly referred to as MPI + X that facilitates migration of our applications to use both coarse grain and fine grain parallelism. Our focus with the applications selected is on the efficacy of algorithms in these applications to take advantage of features like: large number of cores, wide vector units, higher-bandwidth and deeper memory sub-system. This is a first step towards understanding applications, algorithms and programming environments for Trinity and future exascale computing systems.},
doi = {10.2172/1504115},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2015},
month = {1}
}