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Title: Mask Blank Defect Detection

Abstract

Mask blanks are the substrates that hold the master patterns for integrated circuits. Integrated circuits are semiconductor devices, such as microprocessors (mPs), dynamic random access memory (DRAMs), and application specific integrated circuits (ASICs) that are central to the computer, communication, and electronics industries. These devices are fabricated using a set of master patterns that are sequentially imaged onto light-sensitive coated silicon wafers and processed to form thin layers of insulating and conductive materials on top of the wafer. These materials form electrical paths and transistors that control the flow of electricity through the device. For the past forty years the semiconductor industry has made phenomenal improvements in device functionality, compactness, speed, power, and cost. This progress is principally due to the exponential decrease in the minimum feature size of integrated circuits, which has been reduced by a factor of {radical}2 every three years. Since 1992 the Semiconductor Industry Association (SIA) has coordinated the efforts of producing a technology roadmap for semiconductors. In the latest document, ''The International Technology Roadmap for Semiconductors: 1999'', future technology nodes (minimum feature sizes) and targeted dates were specified and are summarized in Table 1. Lithography is the imaging technology for producing a de-magnified image ofmore » the mask on the wafer. A typical de-magnification factor is 4. Mask blank defects as small as one-eighth the equivalent minimum feature size are printable and may cause device failure. Defects might be the result of the surface preparation, such as polishing, or contamination due to handling or the environment. Table 2 shows the maximum tolerable defect sizes on the mask blank for each technology node. This downward trend puts a tremendous burden on mask fabrication, particularly in the area of defect detection and reduction. A new infrastructure for mask inspection will be required to keep pace with this aggressive roadmap. Depending on the specific lithography used for a particular generation, mask inspection specifics may change, but the methodology will essentially remain the same. Mask blanks will have to undergo 100% area inspection for defects larger than the maximum acceptable size. Since masks are becoming a significant cost factor in the ownership of lithography tools, this is a critical step--patterning defective mask blanks would be an economic disaster. Inspection does not necessarily have to be done at the ultraviolet wavelength used for the lithography since defects at the mask blank level will interact with visible light, albeit very weakly. Techniques using visible light are appealing because they are familiar to the user, relatively straightforward to manufacture and safe to use, and when designed properly, extendable over many generations. The technology used in commercial wafer inspection tools is currently the prime candidate for mask blank inspection. It is based on direct detection of scattered light from the defect in one or more directions. Figure 1 shows a typical setup with detectors in both the forward scatter direction (bright-field detection) and away from the specular direction (dark-field detection). In these setups the beam and/or mask blank is scanned to achieve full inspection of the blank. The scattered signal from a defect is therefore a short pulse immersed in the dynamic background scatter from the inherent surface roughness of the mask blank and in the light scattered from the optics and mechanical parts within the instrument. State-of-the-art instruments cannot detect defects smaller than 80 nm, insufficient for the next technology node. The research done over the last year addressed defect detection using a different approach --a heterodyne interference/synchronous detection technique that has the potential of enhanced detection of the scattered light from small defects. This detection is accomplished by directly measuring the amplitude of the electric field of the scattered light using interference of the scattered light with a strong, frequency shifted, local oscillator beam. This technique could provide the basis for new visible light inspection equipment.« less

Authors:
;
Publication Date:
Research Org.:
Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
15013535
Report Number(s):
UCRL-ID-137883
TRN: US200604%%47
DOE Contract Number:  
W-7405-ENG-48
Resource Type:
Technical Report
Country of Publication:
United States
Language:
English
Subject:
42 ENGINEERING; AMPLITUDES; CONTAMINATION; DEFECTS; DETECTION; ELECTRIC FIELDS; ELECTRICITY; INTEGRATED CIRCUITS; MICROPROCESSORS; OPTICS; OSCILLATORS; SEMICONDUCTOR DEVICES; SILICON; SUBSTRATES; TRANSISTORS; VELOCITY; WAVELENGTHS

Citation Formats

Johnson, M A, and Sommargren, G E. Mask Blank Defect Detection. United States: N. p., 2000. Web. doi:10.2172/15013535.
Johnson, M A, & Sommargren, G E. Mask Blank Defect Detection. United States. https://doi.org/10.2172/15013535
Johnson, M A, and Sommargren, G E. Fri . "Mask Blank Defect Detection". United States. https://doi.org/10.2172/15013535. https://www.osti.gov/servlets/purl/15013535.
@article{osti_15013535,
title = {Mask Blank Defect Detection},
author = {Johnson, M A and Sommargren, G E},
abstractNote = {Mask blanks are the substrates that hold the master patterns for integrated circuits. Integrated circuits are semiconductor devices, such as microprocessors (mPs), dynamic random access memory (DRAMs), and application specific integrated circuits (ASICs) that are central to the computer, communication, and electronics industries. These devices are fabricated using a set of master patterns that are sequentially imaged onto light-sensitive coated silicon wafers and processed to form thin layers of insulating and conductive materials on top of the wafer. These materials form electrical paths and transistors that control the flow of electricity through the device. For the past forty years the semiconductor industry has made phenomenal improvements in device functionality, compactness, speed, power, and cost. This progress is principally due to the exponential decrease in the minimum feature size of integrated circuits, which has been reduced by a factor of {radical}2 every three years. Since 1992 the Semiconductor Industry Association (SIA) has coordinated the efforts of producing a technology roadmap for semiconductors. In the latest document, ''The International Technology Roadmap for Semiconductors: 1999'', future technology nodes (minimum feature sizes) and targeted dates were specified and are summarized in Table 1. Lithography is the imaging technology for producing a de-magnified image of the mask on the wafer. A typical de-magnification factor is 4. Mask blank defects as small as one-eighth the equivalent minimum feature size are printable and may cause device failure. Defects might be the result of the surface preparation, such as polishing, or contamination due to handling or the environment. Table 2 shows the maximum tolerable defect sizes on the mask blank for each technology node. This downward trend puts a tremendous burden on mask fabrication, particularly in the area of defect detection and reduction. A new infrastructure for mask inspection will be required to keep pace with this aggressive roadmap. Depending on the specific lithography used for a particular generation, mask inspection specifics may change, but the methodology will essentially remain the same. Mask blanks will have to undergo 100% area inspection for defects larger than the maximum acceptable size. Since masks are becoming a significant cost factor in the ownership of lithography tools, this is a critical step--patterning defective mask blanks would be an economic disaster. Inspection does not necessarily have to be done at the ultraviolet wavelength used for the lithography since defects at the mask blank level will interact with visible light, albeit very weakly. Techniques using visible light are appealing because they are familiar to the user, relatively straightforward to manufacture and safe to use, and when designed properly, extendable over many generations. The technology used in commercial wafer inspection tools is currently the prime candidate for mask blank inspection. It is based on direct detection of scattered light from the defect in one or more directions. Figure 1 shows a typical setup with detectors in both the forward scatter direction (bright-field detection) and away from the specular direction (dark-field detection). In these setups the beam and/or mask blank is scanned to achieve full inspection of the blank. The scattered signal from a defect is therefore a short pulse immersed in the dynamic background scatter from the inherent surface roughness of the mask blank and in the light scattered from the optics and mechanical parts within the instrument. State-of-the-art instruments cannot detect defects smaller than 80 nm, insufficient for the next technology node. The research done over the last year addressed defect detection using a different approach --a heterodyne interference/synchronous detection technique that has the potential of enhanced detection of the scattered light from small defects. This detection is accomplished by directly measuring the amplitude of the electric field of the scattered light using interference of the scattered light with a strong, frequency shifted, local oscillator beam. This technique could provide the basis for new visible light inspection equipment.},
doi = {10.2172/15013535},
url = {https://www.osti.gov/biblio/15013535}, journal = {},
number = ,
volume = ,
place = {United States},
year = {2000},
month = {2}
}