skip to main content
OSTI.GOV title logo U.S. Department of Energy
Office of Scientific and Technical Information

Title: D-DMTD: Digital Dual Mixer Time Difference.

Abstract

The digital design discussed in the following document is inspired by the digital dual mixer time difference circuit and based on the white paper, Digital femtosecond time difference circuit for CERN's timing system [5]. DMTD is originally an analog technique that measures the time difference between two events with high precision using a commercial time interval counter. Our project applies this analog concept to a digital system programmed onto a Microsemi ProASIC3E FPGA (Field- Programmable Gate Array). D-DMTD is a digital system theoretically capable of measuring the time difference between two digital clock signals with very fine resolution (sub-picosecond) using a relatively low frequency counter. The system essentially acts as a digital phase detector with femtosecond time resolution. The main concern with this processing technique is its feasibility and accuracy when implemented on an FPGA. Another concern is the environmentally-induced, horizontal phase noise in the digital signals; this 'litter" jeopardizes the fidelity of the clocks and generates glitches in the signals. Thus, the majority of the work was focused on determining under what conditions the digital design performs optimally and generates the most accurate estimations for the phase shift. This work was funded by Dept. 8736, Telemetry and R&D atmore » Sandia National Laboratories. 1 ACKNOWLEDGEMENTS The authors would like to thank the Telemetry group at Sandia National Laboratories (California site) for providing this project with funding, resources, and feedback. We would also like to thank Robert J. Mariano for his managerial support, Joni Dahl for her administrative support, and the engineers in Mobile 44 for their generous donations of equipment and technical expertise in the fields of FPGA programming and digital design. 2« less

Authors:
; ; ;
Publication Date:
Research Org.:
Sandia National Lab. (SNL-CA), Livermore, CA (United States)
Sponsoring Org.:
USDOE National Nuclear Security Administration (NNSA)
OSTI Identifier:
1494164
Report Number(s):
SAND2017-10097
672174
DOE Contract Number:  
AC04-94AL85000
Resource Type:
Technical Report
Country of Publication:
United States
Language:
English

Citation Formats

Hu, Yalin, Tso, Dustin, Kapai, Sarina, and Feldman, Marc. D-DMTD: Digital Dual Mixer Time Difference.. United States: N. p., 2017. Web. doi:10.2172/1494164.
Hu, Yalin, Tso, Dustin, Kapai, Sarina, & Feldman, Marc. D-DMTD: Digital Dual Mixer Time Difference.. United States. doi:10.2172/1494164.
Hu, Yalin, Tso, Dustin, Kapai, Sarina, and Feldman, Marc. Fri . "D-DMTD: Digital Dual Mixer Time Difference.". United States. doi:10.2172/1494164. https://www.osti.gov/servlets/purl/1494164.
@article{osti_1494164,
title = {D-DMTD: Digital Dual Mixer Time Difference.},
author = {Hu, Yalin and Tso, Dustin and Kapai, Sarina and Feldman, Marc},
abstractNote = {The digital design discussed in the following document is inspired by the digital dual mixer time difference circuit and based on the white paper, Digital femtosecond time difference circuit for CERN's timing system [5]. DMTD is originally an analog technique that measures the time difference between two events with high precision using a commercial time interval counter. Our project applies this analog concept to a digital system programmed onto a Microsemi ProASIC3E FPGA (Field- Programmable Gate Array). D-DMTD is a digital system theoretically capable of measuring the time difference between two digital clock signals with very fine resolution (sub-picosecond) using a relatively low frequency counter. The system essentially acts as a digital phase detector with femtosecond time resolution. The main concern with this processing technique is its feasibility and accuracy when implemented on an FPGA. Another concern is the environmentally-induced, horizontal phase noise in the digital signals; this 'litter" jeopardizes the fidelity of the clocks and generates glitches in the signals. Thus, the majority of the work was focused on determining under what conditions the digital design performs optimally and generates the most accurate estimations for the phase shift. This work was funded by Dept. 8736, Telemetry and R&D at Sandia National Laboratories. 1 ACKNOWLEDGEMENTS The authors would like to thank the Telemetry group at Sandia National Laboratories (California site) for providing this project with funding, resources, and feedback. We would also like to thank Robert J. Mariano for his managerial support, Joni Dahl for her administrative support, and the engineers in Mobile 44 for their generous donations of equipment and technical expertise in the fields of FPGA programming and digital design. 2},
doi = {10.2172/1494164},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2017},
month = {9}
}