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Title: AN ASIC WITH A LOW POWER MULTICHANNEL ADC FOR ENERGY AND TIMING MEASUREMENTS

Abstract

Densely packed gamma-ray imaging and spectroscopy instruments employing high performance multichannel electronics occupy large volume and dissipate excessive power. Therefore, the availability of a low power application specific integrated circuit (ASIC) incorporating multiple channels of ADCs and post processing electronics is of critical importance for nuclear physics (NP) instrumentation. Currently available 12-bit 0.2GSps ADC channel count is usually not exceeding 8. Coarse technologies at 130nm or 180nm node usually used for implementing ADCs do not permit achieving low power consumption and cannot be arrayed on a chip. Thus, a new ADC device is required to satisfy the need of electronics for NP and commercial systems. The research carried out during the Phase I project aimed to prove the feasibility of implementing a 28nm CMOS based 32 channel 12-bit ADC ASIC. Most importantly for NP instrumentation, in addition to including a 32-channel ADC array, our proposed ASIC aims to provide digitized signal post-processing function. In current systems digitized signal post-processing is implemented in FPGAs. Thus, the functionality our ASIC provides is equivalent to the functionality currently realized using 8 ADC parts (each containing 4 channels), an FPGA and a great number of wiring between the ADCs and the FPGA. By usingmore » a single part instead of 9, our solution offers a great reduction in volume, power consumption and cost.« less

Authors:
; ;
Publication Date:
Research Org.:
Pacific Microchip Corp.
Sponsoring Org.:
USDOE Office of Science (SC), High Energy Physics (HEP) (SC-25); USDOE Office of Science (SC), Nuclear Physics (NP) (SC-26)
OSTI Identifier:
1491410
Report Number(s):
DoE-Pacific-0018566
DOE Contract Number:  
SC0018566
Resource Type:
Technical Report
Country of Publication:
United States
Language:
English
Subject:
73 NUCLEAR PHYSICS AND RADIATION PHYSICS

Citation Formats

Karnitski, Anton, Baranauskas, Dalius, and Zelenin, Denis. AN ASIC WITH A LOW POWER MULTICHANNEL ADC FOR ENERGY AND TIMING MEASUREMENTS. United States: N. p., 2019. Web. doi:10.2172/1491410.
Karnitski, Anton, Baranauskas, Dalius, & Zelenin, Denis. AN ASIC WITH A LOW POWER MULTICHANNEL ADC FOR ENERGY AND TIMING MEASUREMENTS. United States. doi:10.2172/1491410.
Karnitski, Anton, Baranauskas, Dalius, and Zelenin, Denis. Mon . "AN ASIC WITH A LOW POWER MULTICHANNEL ADC FOR ENERGY AND TIMING MEASUREMENTS". United States. doi:10.2172/1491410. https://www.osti.gov/servlets/purl/1491410.
@article{osti_1491410,
title = {AN ASIC WITH A LOW POWER MULTICHANNEL ADC FOR ENERGY AND TIMING MEASUREMENTS},
author = {Karnitski, Anton and Baranauskas, Dalius and Zelenin, Denis},
abstractNote = {Densely packed gamma-ray imaging and spectroscopy instruments employing high performance multichannel electronics occupy large volume and dissipate excessive power. Therefore, the availability of a low power application specific integrated circuit (ASIC) incorporating multiple channels of ADCs and post processing electronics is of critical importance for nuclear physics (NP) instrumentation. Currently available 12-bit 0.2GSps ADC channel count is usually not exceeding 8. Coarse technologies at 130nm or 180nm node usually used for implementing ADCs do not permit achieving low power consumption and cannot be arrayed on a chip. Thus, a new ADC device is required to satisfy the need of electronics for NP and commercial systems. The research carried out during the Phase I project aimed to prove the feasibility of implementing a 28nm CMOS based 32 channel 12-bit ADC ASIC. Most importantly for NP instrumentation, in addition to including a 32-channel ADC array, our proposed ASIC aims to provide digitized signal post-processing function. In current systems digitized signal post-processing is implemented in FPGAs. Thus, the functionality our ASIC provides is equivalent to the functionality currently realized using 8 ADC parts (each containing 4 channels), an FPGA and a great number of wiring between the ADCs and the FPGA. By using a single part instead of 9, our solution offers a great reduction in volume, power consumption and cost.},
doi = {10.2172/1491410},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2019},
month = {1}
}