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Title: Multiple core computer processor with globally-accessible local memories

Patent ·
OSTI ID:1489513
; ;

A multi-core computer processor including a plurality of processor cores interconnected in a Network-on-Chip (NoC) architecture, a plurality of caches, each of the plurality of caches being associated with one and only one of the plurality of processor cores, and a plurality of memories, each of the plurality of memories being associated with a different set of at least one of the plurality of processor cores and each of the plurality of memories being configured to be visible in a global memory address space such that the plurality of memories are visible to two or more of the plurality of processor cores.

Research Organization:
Lawrence Berkeley National Laboratory (LBNL), Berkeley, CA (United States)
Sponsoring Organization:
USDOE
DOE Contract Number:
AC02-05CH11231
Assignee:
THE REGENTS OF THE UNIVERSITY OF CALIFORNIA (Oakland, CA)
Patent Number(s):
10,102,179
Application Number:
15/243,634
OSTI ID:
1489513
Resource Relation:
Patent File Date: 2016 Aug 22
Country of Publication:
United States
Language:
English

References (17)

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Systems And Methods For Managing Large Cache Services In A Multi-Core System patent-application June 2011
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Execution Migration patent-application October 2011
Microcontroller having a computing unit and a logic circuit, and method for carrying out computations by a microcontroller for a regulation or a control in a vehicle patent-application November 2011
Control Device And Method For Calculating An Output Parameter For A Controller patent-application May 2013
Energy-Efficient Computing for Extreme-Scale Science journal November 2009

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