Multiple core computer processor with globally-accessible local memories
Patent
·
OSTI ID:1489513
A multi-core computer processor including a plurality of processor cores interconnected in a Network-on-Chip (NoC) architecture, a plurality of caches, each of the plurality of caches being associated with one and only one of the plurality of processor cores, and a plurality of memories, each of the plurality of memories being associated with a different set of at least one of the plurality of processor cores and each of the plurality of memories being configured to be visible in a global memory address space such that the plurality of memories are visible to two or more of the plurality of processor cores.
- Research Organization:
- Lawrence Berkeley National Laboratory (LBNL), Berkeley, CA (United States)
- Sponsoring Organization:
- USDOE
- DOE Contract Number:
- AC02-05CH11231
- Assignee:
- THE REGENTS OF THE UNIVERSITY OF CALIFORNIA (Oakland, CA)
- Patent Number(s):
- 10,102,179
- Application Number:
- 15/243,634
- OSTI ID:
- 1489513
- Country of Publication:
- United States
- Language:
- English
Energy-Efficient Computing for Extreme-Scale Science
|
journal | November 2009 |
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