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Title: Intrinsic use control for system and use controlled component security

Patent ·
OSTI ID:1489512

An Initialization Unit (IU) initiates an initial secure connection with an Intrinsic Use Control (IUC) Chip based on very large random numbers (VLRNs). The IUC Chip in turn initiates a secondary secure connection between it and one or more Use Controlled Components (UCCs). Polling by the IU allows confirmation of an ongoing secure connection, and also allows the IUC Chip to confirm the secondary secure connection to the UCCs. Removal or improper polling response from one of the UCCs results in a response from the IUC Chip that may include notification of tampering, or temporary or permanent discontinued operation of the offending UCC. Permanent discontinued operation may include destruction of the offending UCC, and cascaded discontinued operation of all other UCCs secured by the IUC Chip. A UCC may in turn be another nested layer of IUC Chips, controlling a corresponding layer of UCCs, ad infinitum.

Research Organization:
Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)
Sponsoring Organization:
USDOE
DOE Contract Number:
AC52-07NA27344
Assignee:
Lawrence Livermore National Security, LLC (Livermore, CA)
Patent Number(s):
10,102,382
Application Number:
14/841,116
OSTI ID:
1489512
Resource Relation:
Patent File Date: 2015 Aug 31
Country of Publication:
United States
Language:
English

References (7)

Method for programming a DMA controller in a system on a chip and associated system on a chip patent-application July 2006
Integrated Circuit Chip And Circuit Network patent-application January 2010
Apparatus And Method Of Generating Random Number patent-application September 2010
Non-Deterministic Statistical Data Generator patent-application August 2011
Connection Of Multiple Semiconductor Memory Devices With Chip Enable Function patent-application April 2013
Validating Operation Of System-On-Chip Controller For Storage Device Using Programmable State Machine patent-application June 2014
Memory Controller With Write Data Error Detection And Remediation patent-application August 2014

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