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Title: Impact of Accelerated Stress-Tests on SiC MOSFET Precursor Parameters

Abstract

Integrating SiC power MOSFETs is very attractive for advancing power electronic system performance, yet the system reliability with new devices remains in question. This work presents an overview of accelerated lifetime tests and the packaging and semiconductor failure mechanisms they excite. The experiments explained here includes High Temperature Gate Bias (HTGB), Switching Cycling, Power Cycling, and Thermal Cycling. These experiments stress different failure mechanisms, that show degradation in different device parameters including, but not limited to, threshold voltage and on-resistance. These four experiments help illustrate the spectrum between device and package degradation that can be used to design more reliable power electronic circuits.

Authors:
 [1];  [1];  [2];  [2]
  1. Virginia Polytechnic Institute and State University
  2. National Renewable Energy Laboratory (NREL), Golden, CO (United States)
Publication Date:
Research Org.:
National Renewable Energy Lab. (NREL), Golden, CO (United States)
Sponsoring Org.:
USDOE Office of Energy Efficiency and Renewable Energy (EERE), Advanced Manufacturing Office (EE-5A)
OSTI Identifier:
1489180
Report Number(s):
NREL/CP-5400-73008
DOE Contract Number:  
AC36-08GO28308
Resource Type:
Conference
Resource Relation:
Conference: Presented at the 2018 Second International Symposium on 3D Power Electronics Integration and Manufacturing (3D-PEIM), 25-27 June 2018, College Park, Maryland
Country of Publication:
United States
Language:
English
Subject:
33 ADVANCED PROPULSION SYSTEMS; silicon carbide; MOSFET; degradation; switches; stress; logic gates; reliability

Citation Formats

Kozak, Joseph P., Ngo, Khai D. T., DeVoto, Douglas J, and Major, Joshua. Impact of Accelerated Stress-Tests on SiC MOSFET Precursor Parameters. United States: N. p., 2018. Web. doi:10.1109/3DPEIM.2018.8525234.
Kozak, Joseph P., Ngo, Khai D. T., DeVoto, Douglas J, & Major, Joshua. Impact of Accelerated Stress-Tests on SiC MOSFET Precursor Parameters. United States. doi:10.1109/3DPEIM.2018.8525234.
Kozak, Joseph P., Ngo, Khai D. T., DeVoto, Douglas J, and Major, Joshua. Thu . "Impact of Accelerated Stress-Tests on SiC MOSFET Precursor Parameters". United States. doi:10.1109/3DPEIM.2018.8525234.
@article{osti_1489180,
title = {Impact of Accelerated Stress-Tests on SiC MOSFET Precursor Parameters},
author = {Kozak, Joseph P. and Ngo, Khai D. T. and DeVoto, Douglas J and Major, Joshua},
abstractNote = {Integrating SiC power MOSFETs is very attractive for advancing power electronic system performance, yet the system reliability with new devices remains in question. This work presents an overview of accelerated lifetime tests and the packaging and semiconductor failure mechanisms they excite. The experiments explained here includes High Temperature Gate Bias (HTGB), Switching Cycling, Power Cycling, and Thermal Cycling. These experiments stress different failure mechanisms, that show degradation in different device parameters including, but not limited to, threshold voltage and on-resistance. These four experiments help illustrate the spectrum between device and package degradation that can be used to design more reliable power electronic circuits.},
doi = {10.1109/3DPEIM.2018.8525234},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2018},
month = {11}
}

Conference:
Other availability
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