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Title: Multiple-core computer processor for reverse time migration

Abstract

A multi-core computer processor including a plurality of processor cores interconnected in a Network-on-Chip (NoC) architecture, a plurality of caches, each of the plurality of caches being associated with one and only one of the plurality of processor cores, and a plurality of memories, each of the plurality of memories being associated with a different set of at least one of the plurality of processor cores and each of the plurality of memories being configured to be visible in a global memory address space such that the plurality of memories are visible to two or more of the plurality of processor cores, wherein at least one of a number of the processor cores, a size of each of the plurality of caches, or a size of each of the plurality of memories is configured for performing a reverse-time-migration (RTM) computation.

Inventors:
; ; ; ;
Publication Date:
Research Org.:
Lawrence Berkeley National Lab. (LBNL), Berkeley, CA (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1483256
Patent Number(s):
10,078,593
Application Number:
14/354,502
Assignee:
The Regents of the University of California (Oakland, CA) LBNL
DOE Contract Number:  
AC02-05CH11231
Resource Type:
Patent
Resource Relation:
Patent File Date: 2012 Oct 26
Country of Publication:
United States
Language:
English
Subject:
97 MATHEMATICS AND COMPUTING

Citation Formats

Shalf, John, Donofrio, David, Oliker, Leonid, Kruger, Jens, and Williams, Samuel. Multiple-core computer processor for reverse time migration. United States: N. p., 2018. Web.
Shalf, John, Donofrio, David, Oliker, Leonid, Kruger, Jens, & Williams, Samuel. Multiple-core computer processor for reverse time migration. United States.
Shalf, John, Donofrio, David, Oliker, Leonid, Kruger, Jens, and Williams, Samuel. Tue . "Multiple-core computer processor for reverse time migration". United States. doi:. https://www.osti.gov/servlets/purl/1483256.
@article{osti_1483256,
title = {Multiple-core computer processor for reverse time migration},
author = {Shalf, John and Donofrio, David and Oliker, Leonid and Kruger, Jens and Williams, Samuel},
abstractNote = {A multi-core computer processor including a plurality of processor cores interconnected in a Network-on-Chip (NoC) architecture, a plurality of caches, each of the plurality of caches being associated with one and only one of the plurality of processor cores, and a plurality of memories, each of the plurality of memories being associated with a different set of at least one of the plurality of processor cores and each of the plurality of memories being configured to be visible in a global memory address space such that the plurality of memories are visible to two or more of the plurality of processor cores, wherein at least one of a number of the processor cores, a size of each of the plurality of caches, or a size of each of the plurality of memories is configured for performing a reverse-time-migration (RTM) computation.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Tue Sep 18 00:00:00 EDT 2018},
month = {Tue Sep 18 00:00:00 EDT 2018}
}

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