Ultra-low power processor-in-memory architecture

DeBenedictis, Erik

Title: Ultra-low power processor-in-memory architecture

Patent · Tue Sep 25 00:00:00 EDT 2018

OSTI ID:1482180

DeBenedictis, Erik

An apparatus including a memory array comprising a plurality of rows and a plurality of columns. A switch electrically connects to a particular row of the plurality of rows of the memory array per cycle. An energy storage unit is electrically connected to the memory array through the switch, wherein the energy storage unit is electrically connected in a series with an effective capacitance between ground and the particular row of the plurality of rows of the memory array to which the switch is connected to recycle energy from the memory array.

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Research Organization:: Sandia National Laboratories (SNL), Albuquerque, NM, and Livermore, CA (United States)

Sponsoring Organization:: USDOE

DOE Contract Number:: AC04-94AL85000; NA0003525

Assignee:: National Technology & Engineering Solutions of Sandia, LLC (Albuquerque, NM)

Patent Number(s):: 10,083,080

Application Number:: 15/824,879

OSTI ID:: 1482180

Resource Relation:: Patent File Date: 2017 Nov 28

Country of Publication:: United States

Language:: English

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