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Title: Understanding middle-point inductance's effect on switching transients for multi-chip SiC package design with P-cell/N-cell concept

Abstract

Middle-point inductance L_middle can be introduced in power module designs with P-cell/N-cell concept. In this paper, the effect of middle-point inductance on switching transients is analyzed first using frequency domain analysis. Then a dedicated multiple-chips power module is fabricated with the capability of varying L_middle, and extensive switching tests are conducted to evaluate the device’s switching performance at different L_middle. Experiment results show that as L_middle changes, different voltage stresses are imposed on the active switch and anti-parallel diode. For lower MOSFET’s turn-off, as L_middle goes up, the maximum voltage of lower MOSFET increases; however, the maximum voltage of anti-parallel diode decreases significantly. In addition to voltage spikes, it is observed that the active MOSFET’s turn-on loss will decrease at higher values of L_middle while its turn-off loss will increase. Detailed analysis of this loss variation is presented. The analysis and experiment results will provide design guidelines for multiple-chips power module package design with P-cell/N-cell concept.

Authors:
 [1]; ORCiD logo [2];  [1]; ORCiD logo [2];  [2]; ORCiD logo [2]
  1. The University of Tennessee, Knoxville
  2. ORNL
Publication Date:
Research Org.:
Oak Ridge National Lab. (ORNL), Oak Ridge, TN (United States)
Sponsoring Org.:
USDOE Office of Energy Efficiency and Renewable Energy (EERE)
OSTI Identifier:
1474669
DOE Contract Number:  
AC05-00OR22725
Resource Type:
Conference
Resource Relation:
Conference: 2018 IEEE Applied Power Electronics Conference and Exposition (APEC) - San Antonio, Texas, United States of America - 3/4/2018 5:00:00 AM-3/8/2018 5:00:00 AM
Country of Publication:
United States
Language:
English

Citation Formats

Yang, Fei, Wang, Zhiqiang, Zhang, Zheyu, Campbell, Steven L., Wang, Fei, and Chinthavali, Madhu Sudhan. Understanding middle-point inductance's effect on switching transients for multi-chip SiC package design with P-cell/N-cell concept. United States: N. p., 2018. Web. doi:10.1109/APEC.2018.8341253.
Yang, Fei, Wang, Zhiqiang, Zhang, Zheyu, Campbell, Steven L., Wang, Fei, & Chinthavali, Madhu Sudhan. Understanding middle-point inductance's effect on switching transients for multi-chip SiC package design with P-cell/N-cell concept. United States. doi:10.1109/APEC.2018.8341253.
Yang, Fei, Wang, Zhiqiang, Zhang, Zheyu, Campbell, Steven L., Wang, Fei, and Chinthavali, Madhu Sudhan. Thu . "Understanding middle-point inductance's effect on switching transients for multi-chip SiC package design with P-cell/N-cell concept". United States. doi:10.1109/APEC.2018.8341253. https://www.osti.gov/servlets/purl/1474669.
@article{osti_1474669,
title = {Understanding middle-point inductance's effect on switching transients for multi-chip SiC package design with P-cell/N-cell concept},
author = {Yang, Fei and Wang, Zhiqiang and Zhang, Zheyu and Campbell, Steven L. and Wang, Fei and Chinthavali, Madhu Sudhan},
abstractNote = {Middle-point inductance L_middle can be introduced in power module designs with P-cell/N-cell concept. In this paper, the effect of middle-point inductance on switching transients is analyzed first using frequency domain analysis. Then a dedicated multiple-chips power module is fabricated with the capability of varying L_middle, and extensive switching tests are conducted to evaluate the device’s switching performance at different L_middle. Experiment results show that as L_middle changes, different voltage stresses are imposed on the active switch and anti-parallel diode. For lower MOSFET’s turn-off, as L_middle goes up, the maximum voltage of lower MOSFET increases; however, the maximum voltage of anti-parallel diode decreases significantly. In addition to voltage spikes, it is observed that the active MOSFET’s turn-on loss will decrease at higher values of L_middle while its turn-off loss will increase. Detailed analysis of this loss variation is presented. The analysis and experiment results will provide design guidelines for multiple-chips power module package design with P-cell/N-cell concept.},
doi = {10.1109/APEC.2018.8341253},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2018},
month = {3}
}

Conference:
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