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Title: Dead-time optimization for SiC based voltage source converters using online condition monitoring

Abstract

This paper introduces a dead-time optimization technique for a 2-level voltage source converter (VSC) using turn-off transition monitoring. Dead-time in a VSC impacts power quality, reliability, and efficiency. Silicon carbide (SiC) based VSCs are more sensitive to dead-time from increased reverse conduction losses and turn-off time variability with operating conditions and load characteristics. An online condition monitoring system for SiC devices has been developed using gate drive assist circuits and a micro-controller. It can be leveraged to monitor turn-off time and indicate the optimal dead-time in each switching cycle of any converter operation. It can also be used to specify load current polarity, which is needed for dead-time optimization in an inverter. This is an important distinction from other inverter dead-time elimination/optimization schemes as current around the zero current crossing is hard to accurately detect. A 1kW half-bridge inverter was assembled to test the turn-off time monitoring and dead-time optimization scheme. Results show 91% reduction in reverse conduction power losses in the SiC devices compared to a set dead-time of 500ns switching at 50 kHz.

Authors:
 [1];  [1];  [2];  [2]; ORCiD logo [2];  [2]
  1. The University of Tennessee, Knoxville
  2. ORNL
Publication Date:
Research Org.:
Oak Ridge National Lab. (ORNL), Oak Ridge, TN (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1468923
DOE Contract Number:  
AC05-00OR22725
Resource Type:
Conference
Resource Relation:
Conference: IEEE Workshop on Wide Bandgap Devices and Applications - Albuquerque, New Mexico, United States of America - 11/1/2017 4:00:00 AM-11/3/2017 4:00:00 AM
Country of Publication:
United States
Language:
English

Citation Formats

Dyer, Jacob, Zhang, Zheyu, Wang, Fei, Costinett, Daniel J., Tolbert, Leon M., and Blalock, Benjamin J. Dead-time optimization for SiC based voltage source converters using online condition monitoring. United States: N. p., 2017. Web. doi:10.1109/WiPDA.2017.8170495.
Dyer, Jacob, Zhang, Zheyu, Wang, Fei, Costinett, Daniel J., Tolbert, Leon M., & Blalock, Benjamin J. Dead-time optimization for SiC based voltage source converters using online condition monitoring. United States. https://doi.org/10.1109/WiPDA.2017.8170495
Dyer, Jacob, Zhang, Zheyu, Wang, Fei, Costinett, Daniel J., Tolbert, Leon M., and Blalock, Benjamin J. Wed . "Dead-time optimization for SiC based voltage source converters using online condition monitoring". United States. https://doi.org/10.1109/WiPDA.2017.8170495. https://www.osti.gov/servlets/purl/1468923.
@article{osti_1468923,
title = {Dead-time optimization for SiC based voltage source converters using online condition monitoring},
author = {Dyer, Jacob and Zhang, Zheyu and Wang, Fei and Costinett, Daniel J. and Tolbert, Leon M. and Blalock, Benjamin J.},
abstractNote = {This paper introduces a dead-time optimization technique for a 2-level voltage source converter (VSC) using turn-off transition monitoring. Dead-time in a VSC impacts power quality, reliability, and efficiency. Silicon carbide (SiC) based VSCs are more sensitive to dead-time from increased reverse conduction losses and turn-off time variability with operating conditions and load characteristics. An online condition monitoring system for SiC devices has been developed using gate drive assist circuits and a micro-controller. It can be leveraged to monitor turn-off time and indicate the optimal dead-time in each switching cycle of any converter operation. It can also be used to specify load current polarity, which is needed for dead-time optimization in an inverter. This is an important distinction from other inverter dead-time elimination/optimization schemes as current around the zero current crossing is hard to accurately detect. A 1kW half-bridge inverter was assembled to test the turn-off time monitoring and dead-time optimization scheme. Results show 91% reduction in reverse conduction power losses in the SiC devices compared to a set dead-time of 500ns switching at 50 kHz.},
doi = {10.1109/WiPDA.2017.8170495},
url = {https://www.osti.gov/biblio/1468923}, journal = {},
number = ,
volume = ,
place = {United States},
year = {2017},
month = {11}
}

Conference:
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