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Title: High precision gate signal timing control based active voltage balancing scheme for series-connected fast switching field-effect transistors

Abstract

Due to the low availability, high cost, and limited performance of high voltage power devices in high voltage high power applications, series-connection of low voltage switches is commonly considered. Practically, because of the dynamic voltage unbalance and the resultant reliability issue, switches in series-connection are not popular, especially for fast switching field-effect transistors such as silicon (Si) super junction MOSFETs, silicon carbide (SiC) JFETs, SiC MOSFETs, and gallium nitride (GaN) HEMTs, since their switching performance is highly sensitive to gate control, circuit parasitics, and device parameters. In the end, slight mismatch can introduce severe unbalanced voltage. This paper proposes an active voltage balancing scheme, including 1) tunable gate signal timing unit between series-connected switches with <; 1 ns precision resolution by utilizing a high resolution pulse-width modulator (HRPWM) which has existed in micro-controllers; and 2) online voltage unbalance monitor unit integrated with the gate drive as the feedback. Based on the latest generation 600-V Si CoolMOS, experimental results show that the dynamic voltage can be automatically well balanced in a wide range of operating conditions, and more importantly, the proposed scheme has no penalty for high-speed switching.

Authors:
 [1];  [1];  [1];  [1];  [2]; ORCiD logo [2];  [2];  [2]
  1. The University of Tennessee, Knoxville
  2. ORNL
Publication Date:
Research Org.:
Oak Ridge National Lab. (ORNL), Oak Ridge, TN (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1468921
DOE Contract Number:  
AC05-00OR22725
Resource Type:
Conference
Resource Relation:
Conference: IEEE Applied Power Electronics Conference and Exposition - San Antonio, Texas, United States of America - 3/4/2018 5:00:00 AM-3/8/2018 5:00:00 AM
Country of Publication:
United States
Language:
English

Citation Formats

Zhang, Zheyu, Gui, Handong, Niu, Jiahao, Chen, Ruirui, Wang, Fei, Tolbert, Leon M., Costinett, Daniel J., and Blalock, Benjamin J. High precision gate signal timing control based active voltage balancing scheme for series-connected fast switching field-effect transistors. United States: N. p., 2018. Web. doi:10.1109/APEC.2018.8341125.
Zhang, Zheyu, Gui, Handong, Niu, Jiahao, Chen, Ruirui, Wang, Fei, Tolbert, Leon M., Costinett, Daniel J., & Blalock, Benjamin J. High precision gate signal timing control based active voltage balancing scheme for series-connected fast switching field-effect transistors. United States. doi:10.1109/APEC.2018.8341125.
Zhang, Zheyu, Gui, Handong, Niu, Jiahao, Chen, Ruirui, Wang, Fei, Tolbert, Leon M., Costinett, Daniel J., and Blalock, Benjamin J. Thu . "High precision gate signal timing control based active voltage balancing scheme for series-connected fast switching field-effect transistors". United States. doi:10.1109/APEC.2018.8341125. https://www.osti.gov/servlets/purl/1468921.
@article{osti_1468921,
title = {High precision gate signal timing control based active voltage balancing scheme for series-connected fast switching field-effect transistors},
author = {Zhang, Zheyu and Gui, Handong and Niu, Jiahao and Chen, Ruirui and Wang, Fei and Tolbert, Leon M. and Costinett, Daniel J. and Blalock, Benjamin J.},
abstractNote = {Due to the low availability, high cost, and limited performance of high voltage power devices in high voltage high power applications, series-connection of low voltage switches is commonly considered. Practically, because of the dynamic voltage unbalance and the resultant reliability issue, switches in series-connection are not popular, especially for fast switching field-effect transistors such as silicon (Si) super junction MOSFETs, silicon carbide (SiC) JFETs, SiC MOSFETs, and gallium nitride (GaN) HEMTs, since their switching performance is highly sensitive to gate control, circuit parasitics, and device parameters. In the end, slight mismatch can introduce severe unbalanced voltage. This paper proposes an active voltage balancing scheme, including 1) tunable gate signal timing unit between series-connected switches with <; 1 ns precision resolution by utilizing a high resolution pulse-width modulator (HRPWM) which has existed in micro-controllers; and 2) online voltage unbalance monitor unit integrated with the gate drive as the feedback. Based on the latest generation 600-V Si CoolMOS, experimental results show that the dynamic voltage can be automatically well balanced in a wide range of operating conditions, and more importantly, the proposed scheme has no penalty for high-speed switching.},
doi = {10.1109/APEC.2018.8341125},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2018},
month = {3}
}

Conference:
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