High precision gate signal timing control based active voltage balancing scheme for series-connected fast switching field-effect transistors

Zhang, Zheyu; Gui, Handong; Niu, Jiahao; Chen, Ruirui; Wang, Fei; Tolbert, Leon; Costinett, Daniel; Blalock, Benjamin J.

doi:10.1109/APEC.2018.8341125

Title: High precision gate signal timing control based active voltage balancing scheme for series-connected fast switching field-effect transistors

Conference · Thu Mar 01 00:00:00 EST 2018

DOI:https://doi.org/10.1109/APEC.2018.8341125· OSTI ID:1468921

Zhang, Zheyu ^[1]; Gui, Handong ^[1]; Niu, Jiahao ^[1]; Chen, Ruirui ^[1]; Wang, Fei ^[2];

^[2]; Costinett, Daniel ^[2]; Blalock, Benjamin J. ^[2]

University of Tennessee, Knoxville (UTK)
ORNL

Due to the low availability, high cost, and limited performance of high voltage power devices in high voltage high power applications, series-connection of low voltage switches is commonly considered. Practically, because of the dynamic voltage unbalance and the resultant reliability issue, switches in series-connection are not popular, especially for fast switching field-effect transistors such as silicon (Si) super junction MOSFETs, silicon carbide (SiC) JFETs, SiC MOSFETs, and gallium nitride (GaN) HEMTs, since their switching performance is highly sensitive to gate control, circuit parasitics, and device parameters. In the end, slight mismatch can introduce severe unbalanced voltage. This paper proposes an active voltage balancing scheme, including 1) tunable gate signal timing unit between series-connected switches with <; 1 ns precision resolution by utilizing a high resolution pulse-width modulator (HRPWM) which has existed in micro-controllers; and 2) online voltage unbalance monitor unit integrated with the gate drive as the feedback. Based on the latest generation 600-V Si CoolMOS, experimental results show that the dynamic voltage can be automatically well balanced in a wide range of operating conditions, and more importantly, the proposed scheme has no penalty for high-speed switching.

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Research Organization:: Oak Ridge National Laboratory (ORNL), Oak Ridge, TN (United States)

Sponsoring Organization:: USDOE

DOE Contract Number:: AC05-00OR22725

OSTI ID:: 1468921

Resource Relation:: Conference: IEEE Applied Power Electronics Conference and Exposition - San Antonio, Texas, United States of America - 3/4/2018 5:00:00 AM-3/8/2018 5:00:00 AM

Country of Publication:: United States

Language:: English

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