Architecture for on-die interconnect
Patent
·
OSTI ID:1457407
In an embodiment, an apparatus includes: a plurality of islands configured on a semiconductor die, each of the plurality of islands having a plurality of cores; and a plurality of network switches configured on the semiconductor die and each associated with one of the plurality of islands, where each network switch includes a plurality of output ports, a first set of the output ports are each to couple to the associated network switch of an island via a point-to-point interconnect and a second set of the output ports are each to couple to the associated network switches of a plurality of islands via a point-to-multipoint interconnect. Other embodiments are described and claimed.
- Research Organization:
- Intel Corporation, Santa Clara, CA (United States)
- Sponsoring Organization:
- USDOE
- Assignee:
- Intel Corporation (Santa Clara, CA)
- Patent Number(s):
- 9,998,401
- Application Number:
- 15/042,402
- OSTI ID:
- 1457407
- Country of Publication:
- United States
- Language:
- English
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