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Title: High voltage MOSFET devices and methods of making the devices

Abstract

A SiC MOSFET device having low specific on resistance is described. The device has N+, P-well and JFET regions extended in one direction (Y-direction) and P+ and source contacts extended in an orthogonal direction (X-direction). The polysilicon gate of the device covers the JFET region and is terminated over the P-well region to minimize electric field at the polysilicon gate edge. In use, current flows vertically from the drain contact at the bottom of the structure into the JFET region and then laterally in the X direction through the accumulation region and through the MOSFET channels into the adjacent N+ region. The current flowing out of the channel then flows along the N+ region in the Y-direction and is collected by the source contacts and the final metal. Methods of making the device are also described.

Inventors:
; ;
Publication Date:
Research Org.:
USDOE Advanced Research Projects Agency - Energy (ARPA-E)
Sponsoring Org.:
USDOE
OSTI Identifier:
1455223
Patent Number(s):
9,991,376
Application Number:
14/966,476
Assignee:
Monolith Semiconductor Inc. (Round Rock, TX) ARPA-E
DOE Contract Number:  
AR0000442
Resource Type:
Patent
Resource Relation:
Patent File Date: 2015 Dec 11
Country of Publication:
United States
Language:
English

Citation Formats

Banerjee, Sujit, Matocha, Kevin, and Chatty, Kiran. High voltage MOSFET devices and methods of making the devices. United States: N. p., 2018. Web.
Banerjee, Sujit, Matocha, Kevin, & Chatty, Kiran. High voltage MOSFET devices and methods of making the devices. United States.
Banerjee, Sujit, Matocha, Kevin, and Chatty, Kiran. Tue . "High voltage MOSFET devices and methods of making the devices". United States. doi:. https://www.osti.gov/servlets/purl/1455223.
@article{osti_1455223,
title = {High voltage MOSFET devices and methods of making the devices},
author = {Banerjee, Sujit and Matocha, Kevin and Chatty, Kiran},
abstractNote = {A SiC MOSFET device having low specific on resistance is described. The device has N+, P-well and JFET regions extended in one direction (Y-direction) and P+ and source contacts extended in an orthogonal direction (X-direction). The polysilicon gate of the device covers the JFET region and is terminated over the P-well region to minimize electric field at the polysilicon gate edge. In use, current flows vertically from the drain contact at the bottom of the structure into the JFET region and then laterally in the X direction through the accumulation region and through the MOSFET channels into the adjacent N+ region. The current flowing out of the channel then flows along the N+ region in the Y-direction and is collected by the source contacts and the final metal. Methods of making the device are also described.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Tue Jun 05 00:00:00 EDT 2018},
month = {Tue Jun 05 00:00:00 EDT 2018}
}

Patent:

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