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Efficient accesses of data structures using processing near memory

Patent ·
OSTI ID:1444107
; ;
Systems, apparatuses, and methods for implementing efficient queues and other data structures. A queue may be shared among multiple processors and/or threads without using explicit software atomic instructions to coordinate access to the queue. System software may allocate an atomic queue and corresponding queue metadata in system memory and return, to the requesting thread, a handle referencing the queue metadata. Any number of threads may utilize the handle for accessing the atomic queue. The logic for ensuring the atomicity of accesses to the atomic queue may reside in a management unit in the memory controller coupled to the memory where the atomic queue is allocated.
Research Organization:
Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)
Sponsoring Organization:
USDOE
DOE Contract Number:
AC52-07NA27344
Assignee:
Advanced Micro Devices, Inc. (Santa Clara, CA)
Patent Number(s):
9,977,609
Application Number:
15/063,186
OSTI ID:
1444107
Country of Publication:
United States
Language:
English

References (6)

Fine-grain task aggregation and coordination on GPUs conference June 2014
Accelerating Irregular Algorithms on GPGPUs Using Fine-Grain Hardware Worklists conference December 2014
Atomic-free irregular computations on GPUs
  • Nasre, Rupesh; Burtscher, Martin; Pingali, Keshav
  • GPGPU-6 Proceedings of the 6th Workshop on General Purpose Processor Using Graphics Processing Units, p. 96-107 https://doi.org/10.1145/2458523.2458533
conference January 2013
Data-Driven Versus Topology-driven Irregular Computations on GPUs conference May 2013
A study of Persistent Threads style GPU programming for GPGPU workloads conference May 2012
Fine-grain task aggregation and coordination on GPUs journal October 2014

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