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Title: A Full Mesh ATCA-based General Purpose Data Processing Board (Pulsar II)

Abstract

The Pulsar II is a custom ATCA full mesh enabled FPGA-based processor board which has been designed with the goal of creating a scalable architecture abundant in flexible, non-blocking, high bandwidth interconnections. The design has been motivated by silicon-based tracking trigger needs for LHC experiments. In this technical memo we describe the Pulsar II hardware and its performance, such as the performance test results with full mesh backplanes from different vendors, how the backplane is used for the development of low-latency time-multiplexed data transfer schemes and how the inter-shelf and intra-shelf synchronization works.

Authors:
 [1]
  1. Univ. of Sao Paulo (Brazil); et al.
Publication Date:
Research Org.:
Fermi National Accelerator Lab. (FNAL), Batavia, IL (United States)
Sponsoring Org.:
USDOE Office of Science (SC), High Energy Physics (HEP) (SC-25)
Contributing Org.:
CMS Collaboration
OSTI Identifier:
1431570
Report Number(s):
FERMILAB-TM-2650-E
1662880; TRN: US1801199
DOE Contract Number:  
AC02-07CH11359
Resource Type:
Technical Report
Country of Publication:
United States
Language:
English
Subject:
46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND TECHNOLOGY; CERN LHC; DATA PROCESSING; DESIGN; PERFORMANCE

Citation Formats

Ajuha, S. A Full Mesh ATCA-based General Purpose Data Processing Board (Pulsar II). United States: N. p., 2017. Web. doi:10.2172/1431570.
Ajuha, S. A Full Mesh ATCA-based General Purpose Data Processing Board (Pulsar II). United States. doi:10.2172/1431570.
Ajuha, S. Thu . "A Full Mesh ATCA-based General Purpose Data Processing Board (Pulsar II)". United States. doi:10.2172/1431570. https://www.osti.gov/servlets/purl/1431570.
@article{osti_1431570,
title = {A Full Mesh ATCA-based General Purpose Data Processing Board (Pulsar II)},
author = {Ajuha, S.},
abstractNote = {The Pulsar II is a custom ATCA full mesh enabled FPGA-based processor board which has been designed with the goal of creating a scalable architecture abundant in flexible, non-blocking, high bandwidth interconnections. The design has been motivated by silicon-based tracking trigger needs for LHC experiments. In this technical memo we describe the Pulsar II hardware and its performance, such as the performance test results with full mesh backplanes from different vendors, how the backplane is used for the development of low-latency time-multiplexed data transfer schemes and how the inter-shelf and intra-shelf synchronization works.},
doi = {10.2172/1431570},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Thu Jun 29 00:00:00 EDT 2017},
month = {Thu Jun 29 00:00:00 EDT 2017}
}

Technical Report:

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