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Title: A Time-multiplexed FPGA Overlay with Linear Interconnect

Authors:
; ; ;
Publication Date:
Research Org.:
Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1430932
Report Number(s):
LLNL-CONF-738371
DOE Contract Number:  
AC52-07NA27344
Resource Type:
Conference
Resource Relation:
Conference: Presented at: Design Automation and Test in Europe (DATE), Dresden, Germany, Mar 19 - Mar 23, 2018
Country of Publication:
United States
Language:
English
Subject:
97 MATHEMATICS, COMPUTING, AND INFORMATION SCIENCE; 42 ENGINEERING

Citation Formats

Li, X, Jain, A K, Maskell, D L, and Fahmy, S A. A Time-multiplexed FPGA Overlay with Linear Interconnect. United States: N. p., 2017. Web.
Li, X, Jain, A K, Maskell, D L, & Fahmy, S A. A Time-multiplexed FPGA Overlay with Linear Interconnect. United States.
Li, X, Jain, A K, Maskell, D L, and Fahmy, S A. Thu . "A Time-multiplexed FPGA Overlay with Linear Interconnect". United States. doi:. https://www.osti.gov/servlets/purl/1430932.
@article{osti_1430932,
title = {A Time-multiplexed FPGA Overlay with Linear Interconnect},
author = {Li, X and Jain, A K and Maskell, D L and Fahmy, S A},
abstractNote = {},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Thu Sep 07 00:00:00 EDT 2017},
month = {Thu Sep 07 00:00:00 EDT 2017}
}

Conference:
Other availability
Please see Document Availability for additional information on obtaining the full-text document. Library patrons may search WorldCat to identify libraries that hold this conference proceeding.

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