Low power adaptive synchronizer
Patent
·
OSTI ID:1422725
A circuit adapts to the occurrence of metastable states. The circuit inhibits passing of the metastable state to circuits that follow, by clock gating the output stage. In order to determine whether or not to gate the clock of the output stage, two detect circuits may be used. One circuit detects metastability and another circuit detects metastability resolved to a wrong logic level. The results from one or both detector circuits are used to gate the next clock cycle if needed, waiting for the metastable situation to be resolved.
- Research Organization:
- Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)
- Sponsoring Organization:
- USDOE
- DOE Contract Number:
- AC52-07NA27344
- Assignee:
- Advanced Micro Devices, Inc. (Sunnyvale, CA)
- Patent Number(s):
- 9,899,992
- Application Number:
- 15/239,217
- OSTI ID:
- 1422725
- Country of Publication:
- United States
- Language:
- English
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