skip to main content
OSTI.GOV title logo U.S. Department of Energy
Office of Scientific and Technical Information

Title: Centrally managed unified shared virtual address space

Patent ·
OSTI ID:1420778

Systems, apparatuses, and methods for managing a unified shared virtual address space. A host may execute system software and manage a plurality of nodes coupled to the host. The host may send work tasks to the nodes, and for each node, the host may externally manage the node's view of the system's virtual address space. Each node may have a central processing unit (CPU) style memory management unit (MMU) with an internal translation lookaside buffer (TLB). In one embodiment, the host may be coupled to a given node via an input/output memory management unit (IOMMU) interface, where the IOMMU frontend interface shares the TLB with the given node's MMU. In another embodiment, the host may control the given node's view of virtual address space via memory-mapped control registers.

Research Organization:
Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)
Sponsoring Organization:
USDOE
DOE Contract Number:
AC52-07NA27344
Assignee:
Advanced Micro Devices, Inc. (Sunnyvale, CA)
Patent Number(s):
9,892,058
Application Number:
14/970,940
OSTI ID:
1420778
Resource Relation:
Patent File Date: 2015 Dec 16
Country of Publication:
United States
Language:
English

References (65)

Memory manager for multi-media apparatus and method therefor patent July 2001
Computer graphics processing system, computer memory, and method of use with computer graphics processing system utilizing hierarchical image depth buffer patent April 2006
Concurrent task execution in a multi-processor, single operating system environment patent-application February 2004
Method and apparatus for processing 2D operations in a tiled graphics architecture patent November 2004
Shared Virtual Address Space for Heterogeneous Processors patent-application December 2016
Information processor and multi-hit control method patent-application February 2006
Synchronized two-level graphics processing cache patent November 2004
Method and apparatus for determining texture values of graphical images patent May 2001
Translation lookaside buffer (TLB) arrangement wherein the TLB contents are retained from task when it is swapped out and reloaded when the task is rescheduled patent June 1997
Method and apparatus to power up an integrated device from a low power state patent January 2003
Software controlled cache configuration based on average miss rate patent January 2004
Shared virtual address translation unit for a multiprocessor system patent November 1984
Dynamically Switching A Workload Between Heterogeneous Cores Of A Processor patent-application April 2014
Method for patching virtually aliased pages by a virtual-machine monitor patent May 2007
Pipelined processor operating in different power mode based on branch prediction state of branch history bit encoded as taken weakly not taken and strongly not taken states patent April 1998
Shared translation look-aside buffer and method patent-application December 2006
Coherent visibility sorting and occlusion cycle detection for dynamic aggregate geometry patent July 2001
Hardware driven processor state storage prior to entering a low power mode patent-application June 2009
Multimedia processor employing a shared CPU-graphics cache patent October 2004
System and method for cache sharing patent October 2004
Method and apparatus for remotely placing a computing device into a low power state patent October 2005
Multiprocessor system having controller for controlling the number of processors for which cache coherency must be guaranteed patent October 2003
Z buffer with degree of visibility test patent September 1999
Method for providing power management on multi-threaded processor by using SMM mode to place a physical processor into lower power state patent December 2006
Protocol for transitioning in and out of zero-power state patent September 2011
Memory addressing for a virtual machine implementation on a computer processor supporting virtual hash-page-table searching patent May 2005
Hardware demapping of TLBs shared by multiple threads patent-application March 2007
Method and apparatus for accelerating the rendering of graphical images patent May 2001
Processor power state transistions using separate logic control patent January 2006
Hierarchical Z-buffer visibility
  • Greene, Ned; Kass, Michael; Miller, Gavin
  • Proceedings of the 20th annual conference on Computer graphics and interactive techniques - SIGGRAPH '93 https://doi.org/10.1145/166117.166147
conference January 1993
Tasks distribution in a multi-processor including a translation lookaside buffer shared between processors patent May 2010
System and method for using protection keys to emulate a large region identifier space patent-application December 2006
Software assisted hardware TLB miss handler patent February 1996
Multiprocessing aspects of the PowerPC 601 conference January 1993
CPU and graphics unit with shared cache patent April 2006
Multiprocessor system having mapping table in each node to map global physical addresses to local physical addresses of page copies patent April 1999
Caching TLB translations using a unified page table walker cache patent August 2016
Selective guest system purge control patent October 1988
Lazy TLB consistency for large-scale multiprocessors conference January 1997
Peripheral device feature allowing processors to enter a low power state patent January 2007
System and method for independent invalidation on a per engine basis patent December 2013
Multiple address space mapping technique for shared memory wherein a processor operates a fault handling routine upon a translator miss patent June 1992
Multiple microprocessors with a shared cache patent June 2004
Multiple address space system including address translator for receiving virtual addresses from bus and providing real addresses on the bus patent July 1993
Transitioning a processor package to a low power state patent-application June 2009
Providing Metadata In A Translation Lookaside Buffer (TLB) patent-application August 2011
Managing Translation of a Same Address Across Multiple Contexts Using a Same Entry in a Translation Lookaside Buffer patent-application October 2015
Computer system having shared address space among multiple virtual address spaces patent January 2004
Method of parallel purging of translation lookaside buffer in a multilevel virtual machine system patent November 1996
Method and system for optimally sharing memory between a host processor and graphics processor patent May 2005
Means to share translation lookaside buffer (TLB) entries between different contexts patent-application July 2008
Translation Lookaside Buffer (TLB) with Reserved Areas for Specific Sources patent-application December 2010
Software assisted translation lookaside buffer search mechanism patent January 2013
Shared translation look-aside buffer and method patent July 2008
Using Broadcast-Based TLB Sharing to Reduce Address-Translation Latency in a Shared-Memory System with Electrical Interconnect patent-application February 2014
Providing a low-power state processor voltage in accordance with a detected processor type patent April 2007
Predictive power saving method and apparatus for a device based on computed amount of power saving and time at which the device should transition from first state to second state patent April 2003
Opportunistic sharing of graphics resources to enhance CPU performance in an integrated microprocessor patent January 2005
Hardware demapping of TLBs shared by multiple threads patent June 2008
Systems and methods for accessing a unified translation lookaside buffer patent January 2015
Performing virtual to global address translation in processing subsystem patent-application December 2004
DiDi: Mitigating the Performance Impact of TLB Shootdowns Using a Shared TLB Directory
  • Villavieja, Carlos; Karakostas, Vasileios; Vilanova, Lluis
  • 2011 International Conference on Parallel Architectures and Compilation Techniques https://doi.org/10.1109/PACT.2011.65
conference October 2011
Scalable locality-conscious multithreaded memory allocation
  • Schneider, Scott; Antonopoulos, Christos D.; Nikolopoulos, Dimitrios S.
  • ISMM '06 Proceedings of the 5th international symposium on Memory management, p. 84-94 https://doi.org/10.1145/1133956.1133968
conference January 2006
Multi-node system in which global address generated by processing subsystem includes global to local translation information patent-application December 2004
Processor system including an index buffer circuit and a translation look-aside buffer control circuit for processor-to-processor interfacing patent July 1997

Similar Records

A VLSI chip set for a multiprocessor workstation; Part II: A memory management unit and cache controller
Journal Article · Fri Dec 01 00:00:00 EST 1989 · IEEE Journal of Solid-State Circuits (Institute of Electrical and Electronics Engineers); (USA) · OSTI ID:1420778
+4 more
Efficient local data movement in shared-memory multiprocessor systems
Book · Thu Jan 01 00:00:00 EST 1987 · OSTI ID:1420778
Virtually addressed caches for multiprogramming and multiprocessing environments
Thesis/Dissertation · Tue Jan 01 00:00:00 EST 1985 · OSTI ID:1420778

Related Subjects

97 MATHEMATICS AND COMPUTING