skip to main content
OSTI.GOV title logo U.S. Department of Energy
Office of Scientific and Technical Information

Title: Multithreading in vector processors

Abstract

In one embodiment, a system includes a processor having a vector processing mode and a multithreading mode. The processor is configured to operate on one thread per cycle in the multithreading mode. The processor includes a program counter register having a plurality of program counters, and the program counter register is vectorized. Each program counter in the program counter register represents a distinct corresponding thread of a plurality of threads. The processor is configured to execute the plurality of threads by activating the plurality of program counters in a round robin cycle.

Inventors:
; ;
Publication Date:
Research Org.:
International Business Machines Corporation, Armonk, NY (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1417324
Patent Number(s):
9,870,340
Application Number:
14/672,568
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION (Armonk, NY) OSTI
DOE Contract Number:  
B599858
Resource Type:
Patent
Resource Relation:
Patent File Date: 2015 Mar 30
Country of Publication:
United States
Language:
English
Subject:
97 MATHEMATICS AND COMPUTING

Citation Formats

Evangelinos, Constantinos, Kim, Changhoan, and Nair, Ravi. Multithreading in vector processors. United States: N. p., 2018. Web.
Evangelinos, Constantinos, Kim, Changhoan, & Nair, Ravi. Multithreading in vector processors. United States.
Evangelinos, Constantinos, Kim, Changhoan, and Nair, Ravi. Tue . "Multithreading in vector processors". United States. doi:. https://www.osti.gov/servlets/purl/1417324.
@article{osti_1417324,
title = {Multithreading in vector processors},
author = {Evangelinos, Constantinos and Kim, Changhoan and Nair, Ravi},
abstractNote = {In one embodiment, a system includes a processor having a vector processing mode and a multithreading mode. The processor is configured to operate on one thread per cycle in the multithreading mode. The processor includes a program counter register having a plurality of program counters, and the program counter register is vectorized. Each program counter in the program counter register represents a distinct corresponding thread of a plurality of threads. The processor is configured to execute the plurality of threads by activating the plurality of program counters in a round robin cycle.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Tue Jan 16 00:00:00 EST 2018},
month = {Tue Jan 16 00:00:00 EST 2018}
}

Patent:

Save / Share: