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Title: Processor-in-memory-and-storage architecture

Abstract

A method and apparatus for performing reliable general-purpose computing. Each sub-core of a plurality of sub-cores of a processor core processes a same instruction at a same time. A code analyzer receives a plurality of residues that represents a code word corresponding to the same instruction and an indication of whether the code word is a memory address code or a data code from the plurality of sub-cores. The code analyzer determines whether the plurality of residues are consistent or inconsistent. The code analyzer and the plurality of sub-cores perform a set of operations based on whether the code word is a memory address code or a data code and a determination of whether the plurality of residues are consistent or inconsistent.

Inventors:
Publication Date:
Research Org.:
Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1415442
Patent Number(s):
9,858,144
Application Number:
14/831,711
Assignee:
National Technology & Engineering Solutions of Sandia, LLC (Albuquerque, NM) SNL-A
DOE Contract Number:
AC04-94AL85000
Resource Type:
Patent
Resource Relation:
Patent File Date: 2015 Aug 20
Country of Publication:
United States
Language:
English
Subject:
97 MATHEMATICS AND COMPUTING

Citation Formats

DeBenedictis, Erik. Processor-in-memory-and-storage architecture. United States: N. p., 2018. Web.
DeBenedictis, Erik. Processor-in-memory-and-storage architecture. United States.
DeBenedictis, Erik. Tue . "Processor-in-memory-and-storage architecture". United States. doi:. https://www.osti.gov/servlets/purl/1415442.
@article{osti_1415442,
title = {Processor-in-memory-and-storage architecture},
author = {DeBenedictis, Erik},
abstractNote = {A method and apparatus for performing reliable general-purpose computing. Each sub-core of a plurality of sub-cores of a processor core processes a same instruction at a same time. A code analyzer receives a plurality of residues that represents a code word corresponding to the same instruction and an indication of whether the code word is a memory address code or a data code from the plurality of sub-cores. The code analyzer determines whether the plurality of residues are consistent or inconsistent. The code analyzer and the plurality of sub-cores perform a set of operations based on whether the code word is a memory address code or a data code and a determination of whether the plurality of residues are consistent or inconsistent.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Tue Jan 02 00:00:00 EST 2018},
month = {Tue Jan 02 00:00:00 EST 2018}
}

Patent:

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