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Title: Design and Test of a 65nm CMOS Front-End with Zero Dead Time for Next Generation Pixel Detectors

Abstract

This work is concerned with the experimental characterization of a synchronous analog processor with zero dead time developed in a 65 nm CMOS technology, conceived for pixel detectors at the HL-LHC experiment upgrades. It includes a low noise, fast charge sensitive amplifier with detector leakage compensation circuit, and a compact, single ended comparator able to correctly process hits belonging to two consecutive bunch crossing periods. A 2-bit Flash ADC is exploited for digital conversion immediately after the preamplifier. A description of the circuits integrated in the front-end processor and the initial characterization results are provided

Authors:
 [1];  [2];  [2];  [2];  [2];  [3];  [1];  [1];  [2]
  1. INFN, Pavia
  2. Fermilab
  3. Lyon, IPN
Publication Date:
Research Org.:
Fermi National Accelerator Lab. (FNAL), Batavia, IL (United States)
Sponsoring Org.:
USDOE Office of Science (SC), High Energy Physics (HEP) (SC-25)
OSTI Identifier:
1414398
Report Number(s):
FERMILAB-CONF-17-461-PPD
1644036
DOE Contract Number:  
AC02-07CH11359
Resource Type:
Conference
Country of Publication:
United States
Language:
English
Subject:
46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND TECHNOLOGY

Citation Formats

Gaioni, L., Braga, D., Christian, D., Deptuch, G., Fahim. F., Fahim. F., Nodari, B., Ratti, L., Re, V., and Zimmerman, T. Design and Test of a 65nm CMOS Front-End with Zero Dead Time for Next Generation Pixel Detectors. United States: N. p., 2017. Web.
Gaioni, L., Braga, D., Christian, D., Deptuch, G., Fahim. F., Fahim. F., Nodari, B., Ratti, L., Re, V., & Zimmerman, T. Design and Test of a 65nm CMOS Front-End with Zero Dead Time for Next Generation Pixel Detectors. United States.
Gaioni, L., Braga, D., Christian, D., Deptuch, G., Fahim. F., Fahim. F., Nodari, B., Ratti, L., Re, V., and Zimmerman, T. Fri . "Design and Test of a 65nm CMOS Front-End with Zero Dead Time for Next Generation Pixel Detectors". United States. doi:. https://www.osti.gov/servlets/purl/1414398.
@article{osti_1414398,
title = {Design and Test of a 65nm CMOS Front-End with Zero Dead Time for Next Generation Pixel Detectors},
author = {Gaioni, L. and Braga, D. and Christian, D. and Deptuch, G. and Fahim. F., Fahim. F. and Nodari, B. and Ratti, L. and Re, V. and Zimmerman, T.},
abstractNote = {This work is concerned with the experimental characterization of a synchronous analog processor with zero dead time developed in a 65 nm CMOS technology, conceived for pixel detectors at the HL-LHC experiment upgrades. It includes a low noise, fast charge sensitive amplifier with detector leakage compensation circuit, and a compact, single ended comparator able to correctly process hits belonging to two consecutive bunch crossing periods. A 2-bit Flash ADC is exploited for digital conversion immediately after the preamplifier. A description of the circuits integrated in the front-end processor and the initial characterization results are provided},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Fri Sep 01 00:00:00 EDT 2017},
month = {Fri Sep 01 00:00:00 EDT 2017}
}

Conference:
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