Design and Test of a 65nm CMOS Front-End with Zero Dead Time for Next Generation Pixel Detectors
Conference
·
OSTI ID:1414398
- INFN, Pavia
- Fermilab
- Lyon, IPN
This work is concerned with the experimental characterization of a synchronous analog processor with zero dead time developed in a 65 nm CMOS technology, conceived for pixel detectors at the HL-LHC experiment upgrades. It includes a low noise, fast charge sensitive amplifier with detector leakage compensation circuit, and a compact, single ended comparator able to correctly process hits belonging to two consecutive bunch crossing periods. A 2-bit Flash ADC is exploited for digital conversion immediately after the preamplifier. A description of the circuits integrated in the front-end processor and the initial characterization results are provided
- Research Organization:
- Fermi National Accelerator Lab. (FNAL), Batavia, IL (United States)
- Sponsoring Organization:
- USDOE Office of Science (SC), High Energy Physics (HEP)
- DOE Contract Number:
- AC02-07CH11359
- OSTI ID:
- 1414398
- Report Number(s):
- FERMILAB-CONF-17-461-PPD; 1644036
- Country of Publication:
- United States
- Language:
- English
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