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Title: Scalable polylithic on-package integratable apparatus and method

Abstract

Described is an apparatus which comprises: a first die including: a processing core; a crossbar switch coupled to the processing core; and a first edge interface coupled to the crossbar switch; and a second die including: a first edge interface positioned at a periphery of the second die and coupled to the first edge interface of the first die, wherein the first edge interface of the first die and the first edge interface of the second die are positioned across each other; a clock synchronization circuit coupled to the second edge interface; and a memory interface coupled to the clock synchronization circuit.

Inventors:
; ;
Publication Date:
Research Org.:
Intel Corporation, Santa Clara, CA (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1411393
Patent Number(s):
9,837,391
Application Number:
14/967,231
Assignee:
Intel Corporation (Santa Clara, CA) OSTI
DOE Contract Number:  
B608115
Resource Type:
Patent
Resource Relation:
Patent File Date: 2015 Dec 11
Country of Publication:
United States
Language:
English
Subject:
42 ENGINEERING; 97 MATHEMATICS AND COMPUTING

Citation Formats

Khare, Surhud, Somasekhar, Dinesh, and Borkar, Shekhar Y. Scalable polylithic on-package integratable apparatus and method. United States: N. p., 2017. Web.
Khare, Surhud, Somasekhar, Dinesh, & Borkar, Shekhar Y. Scalable polylithic on-package integratable apparatus and method. United States.
Khare, Surhud, Somasekhar, Dinesh, and Borkar, Shekhar Y. Tue . "Scalable polylithic on-package integratable apparatus and method". United States. doi:. https://www.osti.gov/servlets/purl/1411393.
@article{osti_1411393,
title = {Scalable polylithic on-package integratable apparatus and method},
author = {Khare, Surhud and Somasekhar, Dinesh and Borkar, Shekhar Y.},
abstractNote = {Described is an apparatus which comprises: a first die including: a processing core; a crossbar switch coupled to the processing core; and a first edge interface coupled to the crossbar switch; and a second die including: a first edge interface positioned at a periphery of the second die and coupled to the first edge interface of the first die, wherein the first edge interface of the first die and the first edge interface of the second die are positioned across each other; a clock synchronization circuit coupled to the second edge interface; and a memory interface coupled to the clock synchronization circuit.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Tue Dec 05 00:00:00 EST 2017},
month = {Tue Dec 05 00:00:00 EST 2017}
}

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