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Title: Scalable polylithic on-package integratable apparatus and method

Patent ·
OSTI ID:1411393
; ;

Described is an apparatus which comprises: a first die including: a processing core; a crossbar switch coupled to the processing core; and a first edge interface coupled to the crossbar switch; and a second die including: a first edge interface positioned at a periphery of the second die and coupled to the first edge interface of the first die, wherein the first edge interface of the first die and the first edge interface of the second die are positioned across each other; a clock synchronization circuit coupled to the second edge interface; and a memory interface coupled to the clock synchronization circuit.

Research Organization:
Intel Corporation, Santa Clara, CA (United States)
Sponsoring Organization:
USDOE
DOE Contract Number:
B608115
Assignee:
Intel Corporation (Santa Clara, CA)
Patent Number(s):
9,837,391
Application Number:
14/967,231
OSTI ID:
1411393
Resource Relation:
Patent File Date: 2015 Dec 11
Country of Publication:
United States
Language:
English

References (7)

Memory controller with multi-protocol interface patent January 2013
Layered Crossbar For Interconnection Of Multiple Processors And Shared Memories patent-application September 2007
Forming Multiprocessor Systems Using Dual Processors patent-application July 2012
Final Faulty Core Recovery Mechanisms For A Two-Dimensional Network On A Processor Array patent-application April 2014
Die-Stacked Device With Partitioned Multi-Hop Network patent-application June 2014
On-Package Multiprocessor Ground-Referenced Single-Ended Interconnect patent-application September 2014
Edge-Aware Synchronization Of A Data Signal patent-application June 2016

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