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Title: New Insights into Fully-Depleted SOI Transistor Response During Total-Dose Irradiation

Abstract

Previous work showed the possible existence of a total-dose latch effect in fully-depleted SOI transistors that could severely limit the radiation hardness of SOI devices. Other work showed that worst-case bias configuration during irradiation was the transmission gate bias configuration. In this work we further explore the effects of total-dose ionizing irradiation on fully-depleted SOI transistors. Closed-geometry and standard transistors fabricated in two fully-depleted processes were irradiated with 10-keV x rays. Our results show no evidence for a total-dose latch effect as proposed by others. Instead, in absence of parasitic trench sidewall leakage, our data suggests that the increase in radiation-induced leakage current is caused by positive charge trapping in the buried oxide inverting the back-channel interface. At moderate levels of trapped charge, the back-channel interface is slightly inverted causing a small leakage current to flow. This leakage current is amplified to considerably higher levels by impact ionization. Because the back-channel interface is in weak inversion, the top-gate bias can modulate the back-channel interface and turn the leakage current off at large, negative voltage levels. At high levels of trapped charge, the back-channel interface is fully inverted and the gate bias has little effect on leakage current. However, it ismore » likely that this current also is amplified by impact ionization. For these transistors, the worst-case bias configuration was determined to be the ''ON'' bias configuration. These results have important implication on hardness assurance.« less

Authors:
; ; ; ; ;
Publication Date:
Research Org.:
Sandia National Labs., Albuquerque, NM (US); Sandia National Labs., Livermore, CA (US)
Sponsoring Org.:
US Department of Energy (US)
OSTI Identifier:
14030
Report Number(s):
SAND99-2427C
TRN: US0110953
DOE Contract Number:  
AC04-94AL85000
Resource Type:
Conference
Resource Relation:
Conference: 5th European Conference, RADECS99, Abbaye be Fontevraud (FR), 08/13/1999--08/17/1999; Other Information: PBD: 14 Sep 1999
Country of Publication:
United States
Language:
English
Subject:
46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND TECHNOLOGY; IRRADIATION; LEAKAGE CURRENT; TRANSISTORS; RESPONSE FUNCTIONS; RADIATION HARDENING; X RADIATION

Citation Formats

BURNS,J.A., DODD,PAUL E., KEAST,C.L., SCHWANK,JAMES R., SHANEYFELT,MARTY R., and WYATT,P.W. New Insights into Fully-Depleted SOI Transistor Response During Total-Dose Irradiation. United States: N. p., 1999. Web.
BURNS,J.A., DODD,PAUL E., KEAST,C.L., SCHWANK,JAMES R., SHANEYFELT,MARTY R., & WYATT,P.W. New Insights into Fully-Depleted SOI Transistor Response During Total-Dose Irradiation. United States.
BURNS,J.A., DODD,PAUL E., KEAST,C.L., SCHWANK,JAMES R., SHANEYFELT,MARTY R., and WYATT,P.W. Tue . "New Insights into Fully-Depleted SOI Transistor Response During Total-Dose Irradiation". United States. https://www.osti.gov/servlets/purl/14030.
@article{osti_14030,
title = {New Insights into Fully-Depleted SOI Transistor Response During Total-Dose Irradiation},
author = {BURNS,J.A. and DODD,PAUL E. and KEAST,C.L. and SCHWANK,JAMES R. and SHANEYFELT,MARTY R. and WYATT,P.W.},
abstractNote = {Previous work showed the possible existence of a total-dose latch effect in fully-depleted SOI transistors that could severely limit the radiation hardness of SOI devices. Other work showed that worst-case bias configuration during irradiation was the transmission gate bias configuration. In this work we further explore the effects of total-dose ionizing irradiation on fully-depleted SOI transistors. Closed-geometry and standard transistors fabricated in two fully-depleted processes were irradiated with 10-keV x rays. Our results show no evidence for a total-dose latch effect as proposed by others. Instead, in absence of parasitic trench sidewall leakage, our data suggests that the increase in radiation-induced leakage current is caused by positive charge trapping in the buried oxide inverting the back-channel interface. At moderate levels of trapped charge, the back-channel interface is slightly inverted causing a small leakage current to flow. This leakage current is amplified to considerably higher levels by impact ionization. Because the back-channel interface is in weak inversion, the top-gate bias can modulate the back-channel interface and turn the leakage current off at large, negative voltage levels. At high levels of trapped charge, the back-channel interface is fully inverted and the gate bias has little effect on leakage current. However, it is likely that this current also is amplified by impact ionization. For these transistors, the worst-case bias configuration was determined to be the ''ON'' bias configuration. These results have important implication on hardness assurance.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {1999},
month = {9}
}

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