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Title: Compiling for Application Specific Computational Acceleration in Reconfigurable Architectures Final Report CRADA No. TSB-2033-01

Abstract

The primary objective of this project was to develop memory optimization technology to efficiently deliver data to, and distribute data within, the SRC-6's Field Programmable Gate Array- ("FPGA") based Multi-Adaptive Processors (MAPs). The hardware/software approach was to explore efficient MAP configurations and generate the compiler technology to exploit those configurations. This memory accessing technology represents an important step towards making reconfigurable symmetric multi-processor (SMP) architectures that will be a costeffective solution for large-scale scientific computing.

Authors:
 [1];  [1]
  1. Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States)
Publication Date:
Research Org.:
Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1399732
Report Number(s):
LLNL-TR-739258
DOE Contract Number:  
AC52-07NA27344
Resource Type:
Technical Report
Country of Publication:
United States
Language:
English
Subject:
99 GENERAL AND MISCELLANEOUS; 97 MATHEMATICS, COMPUTING, AND INFORMATION SCIENCE

Citation Formats

De Supinski, B., and Caliga, D.. Compiling for Application Specific Computational Acceleration in Reconfigurable Architectures Final Report CRADA No. TSB-2033-01. United States: N. p., 2017. Web. doi:10.2172/1399732.
De Supinski, B., & Caliga, D.. Compiling for Application Specific Computational Acceleration in Reconfigurable Architectures Final Report CRADA No. TSB-2033-01. United States. doi:10.2172/1399732.
De Supinski, B., and Caliga, D.. Thu . "Compiling for Application Specific Computational Acceleration in Reconfigurable Architectures Final Report CRADA No. TSB-2033-01". United States. doi:10.2172/1399732. https://www.osti.gov/servlets/purl/1399732.
@article{osti_1399732,
title = {Compiling for Application Specific Computational Acceleration in Reconfigurable Architectures Final Report CRADA No. TSB-2033-01},
author = {De Supinski, B. and Caliga, D.},
abstractNote = {The primary objective of this project was to develop memory optimization technology to efficiently deliver data to, and distribute data within, the SRC-6's Field Programmable Gate Array- ("FPGA") based Multi-Adaptive Processors (MAPs). The hardware/software approach was to explore efficient MAP configurations and generate the compiler technology to exploit those configurations. This memory accessing technology represents an important step towards making reconfigurable symmetric multi-processor (SMP) architectures that will be a costeffective solution for large-scale scientific computing.},
doi = {10.2172/1399732},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Thu Sep 28 00:00:00 EDT 2017},
month = {Thu Sep 28 00:00:00 EDT 2017}
}

Technical Report:

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