## Bifurcated method and apparatus for floating point addition with decreased latency time

This patent describes a method for performing floating point addition of a pair of floating point binary numbers each expressed as a mantissa and an exponent. The method comprises the steps of alignment of the mantissas, addition of the aligned mantissas and postnormalization of the mantissa of the sum. The improvement described here comprises: comparing the exponents of the two floating point numbers prior to the alignment step; simultaneously performing two separate calculations along first and second separate parallel paths as follows: calculating a first sum in the first path as if the difference of the exponents is either 0more »