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Title: A performance study of the time-varying cache behavior: a study on APEX, Mantevo, NAS, and PARSEC

Abstract

Cache has long been used to minimize the latency of main memory accesses by storing frequently used data near the processor. Processor performance depends on the underlying cache performance. Therefore, significant research has been done to identify the most crucial metrics of cache performance. Although the majority of research focuses on measuring cache hit rates and data movement as the primary cache performance metrics, cache utilization is significantly important. We investigate the application’s locality using cache utilization metrics. In addition, we present cache utilization and traditional cache performance metrics as the program progresses providing detailed insights into the dynamic application behavior on parallel applications from four benchmark suites running on multiple cores. We explore cache utilization for APEX, Mantevo, NAS, and PARSEC, mostly scientific benchmark suites. Our results indicate that 40% of the data bytes in a cache line are accessed at least once before line eviction. Also, on average a byte is accessed two times before the cache line is evicted for these applications. Moreover, we present runtime cache utilization, as well as, conventional performance metrics that illustrate a holistic understanding of cache behavior. To facilitate this research, we build a memory simulator incorporated into the Structural Simulation Toolkitmore » (Rodrigues et al. in SIGMETRICS Perform Eval Rev 38(4):37–42, 2011). Finally, our results suggest that variable cache line size can result in better performance and can also conserve power.« less

Authors:
 [1];  [2];  [1];  [3]
  1. New Mexico State Univ., Las Cruces, NM (United States). Klipsch School of Electrical and Computer Engineering
  2. Los Alamos National Lab. (LANL), Los Alamos, NM (United States)
  3. Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)
Publication Date:
Research Org.:
Los Alamos National Lab. (LANL), Los Alamos, NM (United States); Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)
Sponsoring Org.:
USDOE Laboratory Directed Research and Development (LDRD) Program; U.S. Army Research Laboratory (ARL); National Science Foundation (NSF)
OSTI Identifier:
1394977
Alternate Identifier(s):
OSTI ID: 1399561
Report Number(s):
LA-UR-17-24198; SAND-2017-8114J
Journal ID: ISSN 0920-8542
Grant/Contract Number:
AC52-06NA25396; W911NF-07-2-0027; AC04-94AL85000
Resource Type:
Journal Article: Accepted Manuscript
Journal Name:
Journal of Supercomputing
Additional Journal Information:
Journal Volume: 74; Journal Issue: 2; Journal ID: ISSN 0920-8542
Publisher:
Springer
Country of Publication:
United States
Language:
English
Subject:
97 MATHEMATICS AND COMPUTING; Cache Utilization; Locality; Workload Characterization; Cache Line Utilization; Multicore Cache Simulation; Runtime Evaluation; Scratchpad; Cache utilization; Workload characterization; Cache line utilization; Multicore cache simulation; Runtime evaluation

Citation Formats

Siddique, Nafiul A., Grubel, Patricia A., Badawy, Abdel-Hameed A., and Cook, Jeanine. A performance study of the time-varying cache behavior: a study on APEX, Mantevo, NAS, and PARSEC. United States: N. p., 2017. Web. doi:10.1007/s11227-017-2144-1.
Siddique, Nafiul A., Grubel, Patricia A., Badawy, Abdel-Hameed A., & Cook, Jeanine. A performance study of the time-varying cache behavior: a study on APEX, Mantevo, NAS, and PARSEC. United States. doi:10.1007/s11227-017-2144-1.
Siddique, Nafiul A., Grubel, Patricia A., Badawy, Abdel-Hameed A., and Cook, Jeanine. Wed . "A performance study of the time-varying cache behavior: a study on APEX, Mantevo, NAS, and PARSEC". United States. doi:10.1007/s11227-017-2144-1.
@article{osti_1394977,
title = {A performance study of the time-varying cache behavior: a study on APEX, Mantevo, NAS, and PARSEC},
author = {Siddique, Nafiul A. and Grubel, Patricia A. and Badawy, Abdel-Hameed A. and Cook, Jeanine},
abstractNote = {Cache has long been used to minimize the latency of main memory accesses by storing frequently used data near the processor. Processor performance depends on the underlying cache performance. Therefore, significant research has been done to identify the most crucial metrics of cache performance. Although the majority of research focuses on measuring cache hit rates and data movement as the primary cache performance metrics, cache utilization is significantly important. We investigate the application’s locality using cache utilization metrics. In addition, we present cache utilization and traditional cache performance metrics as the program progresses providing detailed insights into the dynamic application behavior on parallel applications from four benchmark suites running on multiple cores. We explore cache utilization for APEX, Mantevo, NAS, and PARSEC, mostly scientific benchmark suites. Our results indicate that 40% of the data bytes in a cache line are accessed at least once before line eviction. Also, on average a byte is accessed two times before the cache line is evicted for these applications. Moreover, we present runtime cache utilization, as well as, conventional performance metrics that illustrate a holistic understanding of cache behavior. To facilitate this research, we build a memory simulator incorporated into the Structural Simulation Toolkit (Rodrigues et al. in SIGMETRICS Perform Eval Rev 38(4):37–42, 2011). Finally, our results suggest that variable cache line size can result in better performance and can also conserve power.},
doi = {10.1007/s11227-017-2144-1},
journal = {Journal of Supercomputing},
number = 2,
volume = 74,
place = {United States},
year = {Wed Sep 20 00:00:00 EDT 2017},
month = {Wed Sep 20 00:00:00 EDT 2017}
}

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