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Title: In-memory interconnect protocol configuration registers

Abstract

Systems, apparatuses, and methods for moving the interconnect protocol configuration registers into the main memory space of a node. The region of memory used for storing the interconnect protocol configuration registers may also be made cacheable to reduce the latency of accesses to the interconnect protocol configuration registers. Interconnect protocol configuration registers which are used during a startup routine may be prefetched into the host's cache to make the startup routine more efficient. The interconnect protocol configuration registers for various interconnect protocols may include one or more of device capability tables, memory-side statistics (e.g., to support two-level memory data mapping decisions), advanced memory and interconnect features such as repair resources and routing tables, prefetching hints, error correcting code (ECC) bits, lists of device capabilities, set and store base address, capability, device ID, status, configuration, capabilities, and other settings.

Inventors:
;
Publication Date:
Research Org.:
Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1393431
Patent Number(s):
9,767,028
Application Number:
14/928,981
Assignee:
Advanced Micro Devices, Inc. LLNL
DOE Contract Number:
AC52-07NA27344
Resource Type:
Patent
Resource Relation:
Patent File Date: 2015 Oct 30
Country of Publication:
United States
Language:
English
Subject:
97 MATHEMATICS AND COMPUTING

Citation Formats

Cheng, Kevin Y., and Roberts, David A. In-memory interconnect protocol configuration registers. United States: N. p., 2017. Web.
Cheng, Kevin Y., & Roberts, David A. In-memory interconnect protocol configuration registers. United States.
Cheng, Kevin Y., and Roberts, David A. 2017. "In-memory interconnect protocol configuration registers". United States. doi:. https://www.osti.gov/servlets/purl/1393431.
@article{osti_1393431,
title = {In-memory interconnect protocol configuration registers},
author = {Cheng, Kevin Y. and Roberts, David A.},
abstractNote = {Systems, apparatuses, and methods for moving the interconnect protocol configuration registers into the main memory space of a node. The region of memory used for storing the interconnect protocol configuration registers may also be made cacheable to reduce the latency of accesses to the interconnect protocol configuration registers. Interconnect protocol configuration registers which are used during a startup routine may be prefetched into the host's cache to make the startup routine more efficient. The interconnect protocol configuration registers for various interconnect protocols may include one or more of device capability tables, memory-side statistics (e.g., to support two-level memory data mapping decisions), advanced memory and interconnect features such as repair resources and routing tables, prefetching hints, error correcting code (ECC) bits, lists of device capabilities, set and store base address, capability, device ID, status, configuration, capabilities, and other settings.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = 2017,
month = 9
}

Patent:

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