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Title: VIPRAM_L1CMS: a 2-Tier 3D Architecture for Pattern Recognition for Track Finding

Abstract

In HEP tracking trigger applications, flagging an individual detector hit is not important. Rather, the path of a charged particle through many detector layers is what must be found. Moreover, given the increased luminosity projected for future LHC experiments, this type of track finding will be required within the Level 1 Trigger system. This means that future LHC experiments require not just a chip capable of high-speed track finding but also one with a high-speed readout architecture. VIPRAM_L1CMS is 2-Tier Vertically Integrated chip designed to fulfill these requirements. It is a complete pipelined Pattern Recognition Associative Memory (PRAM) architecture including pattern recognition, result sparsification, and readout for Level 1 trigger applications in CMS with 15-bit wide detector addresses and eight detector layers included in the track finding. Pattern recognition is based on classic Content Addressable Memories with a Current Race Scheme to reduce timing complexity and a 4-bit Selective Precharge to minimize power consumption. VIPRAM_L1CMS uses a pipelined set of priority-encoded binary readout structures to sparsify and readout active road flags at frequencies of at least 100MHz. VIPRAM_L1CMS is designed to work directly with the Pulsar2b Architecture.

Authors:
 [1];  [2];  [1];  [1];  [1]
  1. Fermilab
  2. Northwestern U.
Publication Date:
Research Org.:
Fermi National Accelerator Lab. (FNAL), Batavia, IL (United States)
Sponsoring Org.:
USDOE Office of Science (SC), High Energy Physics (HEP) (SC-25)
OSTI Identifier:
1390182
Report Number(s):
FERMILAB-CONF-16-690-PPD
1622970
DOE Contract Number:
AC02-07CH11359
Resource Type:
Conference
Resource Relation:
Conference: 2017 IEEE Nuclear Science Symposium and Medical Imaging Conference, Atlanta, Georgia, USA, 10/21-10/28/2017
Country of Publication:
United States
Language:
English
Subject:
46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND TECHNOLOGY

Citation Formats

Hoff, J. R., Joshi, Joshi,S., Liu, Liu,, Olsen, J., and Shenai, A. VIPRAM_L1CMS: a 2-Tier 3D Architecture for Pattern Recognition for Track Finding. United States: N. p., 2017. Web.
Hoff, J. R., Joshi, Joshi,S., Liu, Liu,, Olsen, J., & Shenai, A. VIPRAM_L1CMS: a 2-Tier 3D Architecture for Pattern Recognition for Track Finding. United States.
Hoff, J. R., Joshi, Joshi,S., Liu, Liu,, Olsen, J., and Shenai, A. Thu . "VIPRAM_L1CMS: a 2-Tier 3D Architecture for Pattern Recognition for Track Finding". United States. doi:. https://www.osti.gov/servlets/purl/1390182.
@article{osti_1390182,
title = {VIPRAM_L1CMS: a 2-Tier 3D Architecture for Pattern Recognition for Track Finding},
author = {Hoff, J. R. and Joshi, Joshi,S. and Liu, Liu, and Olsen, J. and Shenai, A.},
abstractNote = {In HEP tracking trigger applications, flagging an individual detector hit is not important. Rather, the path of a charged particle through many detector layers is what must be found. Moreover, given the increased luminosity projected for future LHC experiments, this type of track finding will be required within the Level 1 Trigger system. This means that future LHC experiments require not just a chip capable of high-speed track finding but also one with a high-speed readout architecture. VIPRAM_L1CMS is 2-Tier Vertically Integrated chip designed to fulfill these requirements. It is a complete pipelined Pattern Recognition Associative Memory (PRAM) architecture including pattern recognition, result sparsification, and readout for Level 1 trigger applications in CMS with 15-bit wide detector addresses and eight detector layers included in the track finding. Pattern recognition is based on classic Content Addressable Memories with a Current Race Scheme to reduce timing complexity and a 4-bit Selective Precharge to minimize power consumption. VIPRAM_L1CMS uses a pipelined set of priority-encoded binary readout structures to sparsify and readout active road flags at frequencies of at least 100MHz. VIPRAM_L1CMS is designed to work directly with the Pulsar2b Architecture.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Thu Jun 15 00:00:00 EDT 2017},
month = {Thu Jun 15 00:00:00 EDT 2017}
}

Conference:
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