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Title: Store operations to maintain cache coherence

Abstract

In one embodiment, a computer-implemented method includes encountering a store operation during a compile-time of a program, where the store operation is applicable to a memory line. It is determined, by a computer processor, that no cache coherence action is necessary for the store operation. A store-without-coherence-action instruction is generated for the store operation, responsive to determining that no cache coherence action is necessary. The store-without-coherence-action instruction specifies that the store operation is to be performed without a cache coherence action, and cache coherence is maintained upon execution of the store-without-coherence-action instruction.

Inventors:
; ;
Publication Date:
Research Org.:
INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1373722
Patent Number(s):
9,720,832
Application Number:
14/671,050
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION OSTI
DOE Contract Number:  
B599858
Resource Type:
Patent
Resource Relation:
Patent File Date: 2015 Mar 27
Country of Publication:
United States
Language:
English
Subject:
97 MATHEMATICS AND COMPUTING

Citation Formats

Evangelinos, Constantinos, Nair, Ravi, and Ohmacht, Martin. Store operations to maintain cache coherence. United States: N. p., 2017. Web.
Evangelinos, Constantinos, Nair, Ravi, & Ohmacht, Martin. Store operations to maintain cache coherence. United States.
Evangelinos, Constantinos, Nair, Ravi, and Ohmacht, Martin. Tue . "Store operations to maintain cache coherence". United States. doi:. https://www.osti.gov/servlets/purl/1373722.
@article{osti_1373722,
title = {Store operations to maintain cache coherence},
author = {Evangelinos, Constantinos and Nair, Ravi and Ohmacht, Martin},
abstractNote = {In one embodiment, a computer-implemented method includes encountering a store operation during a compile-time of a program, where the store operation is applicable to a memory line. It is determined, by a computer processor, that no cache coherence action is necessary for the store operation. A store-without-coherence-action instruction is generated for the store operation, responsive to determining that no cache coherence action is necessary. The store-without-coherence-action instruction specifies that the store operation is to be performed without a cache coherence action, and cache coherence is maintained upon execution of the store-without-coherence-action instruction.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Tue Aug 01 00:00:00 EDT 2017},
month = {Tue Aug 01 00:00:00 EDT 2017}
}

Patent:

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Works referenced in this record:

Automatic software cache coherence through vectorization
conference, January 1992


The IBM RISC System/6000 processor: Hardware overview
journal, January 1990

  • Bakoglu, H. B.; Grohoski, G. F.; Montoye, R. K.
  • IBM Journal of Research and Development, Vol. 34, Issue 1, p. 12-22
  • DOI: 10.1147/rd.341.0012

Cohesion: a hybrid memory model for accelerators
conference, January 2010